PRELIMINARY
Advanced
Micro
Am5 86™
X
Microprocessor Family
Devices
DISTINCTIVE CHARACTERISTICS
■ Complete 32-Bit Architecture
— Address and data buses
— All registers
■ High-Performance Design
— Industry-standard write-back cache support
— Frequent instructions execute in one clock
— 105.6-million bytes/second burst bus at 33 MHz
— 8-, 16-, and 32-bit data types
■ Standard Features
— Flexible write-through and write-back address
control
— 3-V core with 5-V tolerant I/O
— Available in a 133-MHz version
— Binary compatible with all Am486®DX,
— Advanced 0.35-µ CMOS-process technology
— Dynamic bus sizing for 8-, 16-, and 32-bit buses
— Supports “soft reset” capability
Am486DX2, and Am486DX4 microprocessors
■ High On-Chip Integration
— Wide range of chipsets and support available
through the AMD FusionPCSM Program
— 16-Kbyte unified code and data cache
— Floating-point unit
■ 168-pin PGA package or 208-pin SQFP package
■ IEEE 1149.1 JTAG Boundary-Scan Compatibility
— Paged, virtual memory management
■ Enhanced System and Power Management
■ Supports Environmental Protection Agency's
Energy Star program
— Stop clock control for reduced power
— 3-V operation reduces power consumption up to
40%
consumption
— Industry-standard two-pin System Management
Interrupt (SMI) for power management indepen-
dent of processor operating mode and operating
system
— Energy management capability provides excel-
lent base for energy-efficient design
— Works with a variety of energy-efficient, power-
managed devices
— Static design with Auto Halt power-down support
— Wide range of chipsets supporting SMM avail-
able to allow product differentiation
GENERAL DESCRIPTION
Table 1. Clocking Options
Operating
TheAm5X86™microprocessorisan addition to the AMD
microprocessor product family. The new processor en-
hances system performance by raising the microproces-
sor operating frequency to the highest levels allowed by
current manufacturing technology, while maintaining
complete compatibility with the standard Am486 proces-
sor architecture and Microsoft® Windows®. The CPUs
incorporate write-back cache, flexible clock control, and
enhanced SMM. Table 1 shows available processors
in the Am5X86 microprocessor family.
Input Clock
Available Package
Frequency
133 MHz
133 MHz
33 MHz
33 MHz
168-pin PGA
208-pin SQFP
The Am5X86 microprocessor family allows write-back
configuration through software and cacheable access
control. On-chip cache lines are configurable as either
write-through or write-back. The CPU clock control fea-
ture permits the CPU clock to be stopped under con-
trolled conditions, allowing reduced power consumption
duringsysteminactivity.TheSMMfunctionisimplement-
ed with an industry standard two-pin interface.
This document contains information on a product under development at Advanced Micro Devices. The information is
intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication # 19751 Rev: C Amendment/0
Issue Date: March 1996
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