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AM28F256A-90JC PDF预览

AM28F256A-90JC

更新时间: 2024-09-15 22:56:31
品牌 Logo 应用领域
超微 - AMD 闪存
页数 文件大小 规格书
35页 431K
描述
256 Kilobit (32 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms

AM28F256A-90JC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFJ包装说明:QCCJ, LDCC32,.5X.6
针数:32Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.89最长访问时间:90 ns
其他特性:100K WRITE/ERASE CYCLES MIN命令用户界面:YES
数据轮询:YESJESD-30 代码:R-PQCC-J32
JESD-609代码:e0内存密度:262144 bit
内存集成电路类型:FLASH内存宽度:8
功能数量:1端子数量:32
字数:32768 words字数代码:32000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:32KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC32,.5X.6
封装形状:RECTANGULAR封装形式:CHIP CARRIER
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V编程电压:12 V
认证状态:Not Qualified最大待机电流:0.0001 A
子类别:Flash Memories最大压摆率:0.03 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED切换位:YES
类型:NOR TYPEBase Number Matches:1

AM28F256A-90JC 数据手册

 浏览型号AM28F256A-90JC的Datasheet PDF文件第2页浏览型号AM28F256A-90JC的Datasheet PDF文件第3页浏览型号AM28F256A-90JC的Datasheet PDF文件第4页浏览型号AM28F256A-90JC的Datasheet PDF文件第5页浏览型号AM28F256A-90JC的Datasheet PDF文件第6页浏览型号AM28F256A-90JC的Datasheet PDF文件第7页 
FINAL  
Am28F256A  
256 Kilobit (32 K x 8-Bit)  
CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms  
DISTINCTIVE CHARACTERISTICS  
High performance  
Embedded Erase Electrical Bulk Chip-Erase  
— Access times as fast as 70 ns  
CMOS low power consumption  
— 30 mA maximum active current  
— 100 µA maximum standby current  
— No data retention power consumption  
— 1.5 seconds typical chip-erase including  
pre-programming  
Embedded Program  
— 14 µs typical byte-program including time-out  
— 0.5 second typical chip program  
Command register architecture for  
microprocessor/microcontroller compatible  
write interface  
Compatible with JEDEC-standard byte-wide  
32-Pin EPROM pinouts  
— 32-pin PDIP  
On-chip address and data latches  
— 32-pin PLCC  
Advanced CMOS flash memory technology  
— Low cost single transistor memory cell  
— 32-pin TSOP  
100,000 write/erase cycles minimum  
Write and erase voltage 12.0 V ±5%  
Latch-up protected to 100 mA from –1 V to  
Embedded algorithms for completely  
self-timed write/erase operations  
V
+1 V  
CC  
GENERAL DESCRIPTION  
The Am28F256A is a 256 K Flash memory organized  
as 32 Kbytes of 8 bits each. AMD’s Flash memories  
offer the most cost-effective and reliable read/write  
non- volatile random access memory. The Am28F256A  
is packaged in 32-pin PDIP, PLCC, and TSOP versions.  
It is designed to be reprogrammed and erased in-sys-  
tem or in standard EPROM programmers. The  
Am28F256A is erased when shipped from the factory.  
programming mechanisms. In addition, the combina-  
tion of advanced tunnel oxide processing and low inter-  
nal electric fields for erase and programming  
operations produces reliable cycling. The Am28F256A  
uses a 12.0V±5% VPP high voltage input to perform  
the erase and programming functions.  
The highest degree of latch-up protection is achieved  
with AMD’s proprietary non-epi process. Latch-up pro-  
tection is provided for stresses up to 100 milliamps on  
address and data pins from –1 V to VCC +1 V.  
The standard Am28F256A offers access times as fast  
as 70 ns, allowing operation of high-speed micropro-  
cessors without wait states. To eliminate bus conten-  
tion, the Am28F256A has separate chip enable (CE#)  
and output enable (OE#) controls.  
Embedded Program  
The Am28F256A is byte programmable using the  
Embedded Programming algorithm. The Embedded  
Programming algorithm does not require the system to  
time-out or verify the data programmed. The typical  
room temperature programming time of the  
Am28F256A is one half second.  
AMD’s Flash memories augment EPROM functionality  
with in-circuit electrical erasure and programming. The  
Am28F256A uses a command register to manage this  
functionality, while maintaining a standard JEDEC  
Flash Standard 32-pin pinout. The command register  
allows for 100% TTL level control inputs and fixed  
power supply levels during erase and programming.  
Embedded Erase  
The entire chip is bulk erased using the Embedded  
Erase algorithm. The Embedded Erase algorithm  
automatically programs the entire array prior to electrical  
erase. The timing and verification of electrical erase are  
AMD’s Flash technology reliably stores memory con-  
tents even after 100,000 erase and program cycles.  
The AMD cell is designed to optimize the erase and  
Publication# 18879 Rev: C Amendment/+2  
Issue Date: May 1998  

AM28F256A-90JC 替代型号

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