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AM27C020-150DC PDF预览

AM27C020-150DC

更新时间: 2024-09-12 23:28:43
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其他 - ETC 可编程只读存储器电动程控只读存储器
页数 文件大小 规格书
13页 56K
描述
IC-2MB CMOS EPROM

AM27C020-150DC 数据手册

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FINAL  
Am27C020  
2 Megabit (262,144 x 8-Bit) CMOS EPROM  
DISTINCTIVE CHARACTERISTICS  
Fast access time  
100% Flashrite programming  
— 55 ns maximum access time  
Low power consumption  
Typical programming time of 32 seconds  
Latch-up protected to 100 mA from –1 V to  
V
+ 1 V  
— 100 µA typical CMOS standby current  
JEDEC-approved pinout  
CC  
High noise immunity  
Versatile features for simple interfacing  
— Both CMOS and TTL input/output compatibility  
Two line control functions  
— Plug in upgrade of 1 Mbit EPROM  
— Easy upgrade from 28-pin JEDEC EPROMs  
Single +5 V power supply  
Compact 32-pin DIP, PDIP,TSOP, and PLCC  
±10% power supply tolerance available  
packages  
GENERAL DESCRIPTION  
The Am27C020 is a 2 Mbit, ultraviolet erasable program-  
mable read-only memory. It is organized as 256K words  
by 8 bits per word, operates from a single +5 V supply,  
has a static standby mode, and features fast single ad-  
dress location programming. Products are available in  
windowed ceramic DIP packages, as well as plastic  
one-time programmable (OTP) including TSOP, PLCC,  
and PDIP.  
controls, thus eliminating bus contention in a multiple  
bus microprocessor system.  
AMD’s CMOS process technology provides high speed,  
low power, and high noise immunity. Typical power con-  
sumption is only 100 mW in active mode, and 100 µW in  
standby mode.  
All signals are TTL levels, including programming sig-  
nals. Bit locations may be programmed singly, in blocks,  
or at random.The Am27C020 supports AMD’s Flashrite  
programming algorithm (100 µs pulses) resulting in typ-  
ical programming times of 32 seconds.  
Typically, any byte can be accessed in less than 70 ns,  
allowing operation with high-performance microproces-  
sors without any WAIT states. The Am27C020 offers  
separate Output Enable (OE) and Chip Enable (CE)  
BLOCK DIAGRAM  
Data Outputs  
DQ0–DQ7  
V
V
PP  
CC  
V
SS  
Output Enable  
Chip Enable  
and  
OE  
Output  
Buffers  
CE  
PGM  
Prog Logic  
Y
Y
Gating  
Decoder  
A0–A17  
Address  
Inputs  
X
2,097,152-Bit  
Cell Matrix  
Decoder  
11507H-1  
Publication# 11507 Rev: H Amendment/0  
Issue Date: August 1997  

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