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AM1802

更新时间： 2024-11-24 12:50:35
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德州仪器 - TI 微处理器
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180页 1235K
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AM1802 ARM Microprocessor

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AM1802 数据手册

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AM1802  
www.ti.com  
SPRS710C –NOVEMBER 2010–REVISED MARCH 2012  
AM1802 ARM Microprocessor  
Check for Samples: AM1802  
1 Device Summary  
1.1 Features  
12  
•
•
•
NOR (8-/16-Bit-Wide Data)  
NAND (8-/16-Bit-Wide Data)  
16-Bit SDRAM With 128 MB Address  
Space  
• Highlights  
– 300-MHz ARM926EJ-S™ RISC Core  
– ARM9 Memory Architecture  
– Enhanced Direct-Memory-Access Controller  
3 (EDMA3)  
– DDR2/Mobile DDR Memory Controller  
•
16-Bit DDR2 SDRAM With 512 MB  
Address Space or  
16-Bit mDDR SDRAM With 256 MB  
Address Space  
– Two External Memory Interfaces  
– Three Configurable 16550 type UART  
Modules  
•
– Two Serial Peripheral Interfaces (SPI)  
• Three Configurable 16550 type UART Modules:  
– With Modem Control Signals  
– 16-byte FIFO  
– 16x or 13x Oversampling Option  
• Two Serial Peripheral Interfaces (SPI) Each  
With Multiple Chip-Selects  
• One Multimedia Card (MMC)/Secure Digital (SD)  
Card Interface with Secure Data I/O (SDIO)  
Interfaces  
• One Master/Slave Inter-Integrated Circuit (I2C  
Bus™)  
– Multimedia Card (MMC)/Secure Digital (SD)  
Card Interface with Secure Data I/O (SDIO)  
– One Master/Slave Inter-Integrated Circuit  
– USB 2.0 OTG Port With Integrated PHY  
– One Multichannel Audio Serial Port  
– 10/100 Mb/s Ethernet MAC (EMAC)  
– Three 64-Bit General-Purpose Timers  
– One 64-bit General-Purpose/Watchdog Timer  
• 300-MHz ARM926EJ-S RISC MPU  
• ARM926EJ-S Core  
• USB 2.0 OTG Port With Integrated PHY (USB0)  
– USB 2.0 High-/Full-Speed Client  
– USB 2.0 High-/Full-/Low-Speed Host  
– End Point 0 (Control)  
– End Points 1,2,3,4 (Control, Bulk, Interrupt or  
ISOC) Rx and Tx  
• One Multichannel Audio Serial Port:  
– Transmit/Receive Clocks  
– 32-Bit and 16-Bit (Thumb®) Instructions  
– Single Cycle MAC  
– ARM® Jazelle® Technology  
– EmbeddedICE-RT™ for Real-Time Debug  
• ARM9 Memory Architecture  
– 16K-Byte Instruction Cache  
– 16K-Byte Data Cache  
– Two Clock Zones and 16 Serial Data Pins  
– Supports TDM, I2S, and Similar Formats  
– DIT-Capable  
– 8K-Byte RAM (Vector Table)  
– 64K-Byte ROM  
• Enhanced Direct-Memory-Access Controller 3  
(EDMA3):  
– FIFO buffers for Transmit and Receive  
• 10/100 Mb/s Ethernet MAC (EMAC):  
– IEEE 802.3 Compliant  
– 2 Channel Controllers  
– 3 Transfer Controllers  
– 64 Independent DMA Channels  
– 16 Quick DMA Channels  
– MII Media Independent Interface  
– RMII Reduced Media Independent Interface  
– Management Data I/O (MDIO) Module  
– Programmable Transfer Burst Size  
• 128K-Byte On-chip Memory  
• Real-Time Clock With 32-kHz Oscillator and  
Separate Power Rail  
• 1.8V or 3.3V LVCMOS IOs (except for USB and  
DDR2 interfaces)  
• Three 64-Bit General-Purpose Timers (Each  
Configurable as Two 32-Bit Timers)  
• Two External Memory Interfaces:  
• One 64-Bit General-Purpose/Watchdog Timer  
(Configurable as Two 32-Bit General-Purpose  
– EMIFA  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date. Products conform to  
specifications per the terms of the Texas Instruments standard warranty. Production  
processing does not necessarily include testing of all parameters.  
Copyright © 2010–2012, Texas Instruments Incorporated  
 
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