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AK594096BSP-70 PDF预览

AK594096BSP-70

更新时间: 2024-09-17 23:28:23
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其他 - ETC 动态存储器
页数 文件大小 规格书
2页 79K
描述
x(8+1) Fast Page Mode DRAM Module

AK594096BSP-70 数据手册

 浏览型号AK594096BSP-70的Datasheet PDF文件第2页 
Accutek  
Microcircuit  
Corporation  
AK594096BS / AK594096BG  
4,194,304 Word by 9 Bit CMOS  
Dynamic Random Access Memory  
Front View  
30-Pin SIM  
DESCRIPTION  
The Accutek AK594096 high density memory module is a CMOS  
random access memory organized in 4 Meg x 9 bit words. The as-  
sembly consists of two 4 Meg x 4 and one 4 Meg x 1 DRAMs,  
mounted on the front side of a printed circuit board in 30 pad SIM  
(leadless) or 30 pin SIP (leaded) configuration with  
JEDEC-standard pinouts. Designed especially for low-height appli-  
cations such as VMEbus boards, this low profile module is 0.550  
inch high.  
+
+
1
30  
30-Pin SIP  
+
1
+
The operation is identical to nine 4 Meg x 1 DRAMs. For the lower  
eight bits, data input is tied to data output and brought out sepa-  
rately for each bit, with common RAS and CAS control. This com-  
mon I/O feature dictates the use of early-write cycles to prevent  
contention of data In and data out. Since the Write-Enable (WE)i  
signal must always go low before CAS in a write cycle, Read-Write  
and Read-Modify-Write operation is not possible. For the ninth bit,  
data in (D9) and data out (Q9) pins are brought our separately and  
controlled by a separate PCAS for that bit  
· Power  
1.450 Watt Max Active, 70 nSEC  
1.610 Watt Max Active, 60 nSEC  
16.5 mWatt Max Standy  
FEATURES  
· 4,194,304 x 9 bit organization  
· Operating free air temperature 00C to 700C  
· Low Profile 30 pad (SIM) Single In-Line Memory  
· Low Profile 30 pin (SIP) Single In-Line package  
· JEDEC standard pinout  
· Downward compatible with AK591024 and AK59256  
· Upward compatible with AK5916384  
· Common CAS, RAS and WE for the lower eight bits  
· CAS-before-RAS refresh  
· Fast Page Mode and Static Column Mode versions available,  
nibble mode is not possible  
· Refresh cycle 2048 cycles in 32 mSEC  
PIN NOMENCLATURE  
PIN ASSIGNMENT  
FUNCTIONAL DIAGRAM  
A0 - A10  
A0 - A10  
RAS0  
CAS  
WE  
Address Inputs  
+
A0 - A10  
RAS  
CAS  
WE  
DQ1  
DQ2  
DQ3  
DQ4  
11  
RAS  
CAS  
WE  
1
2
Vcc  
CAS  
DQ1  
A0  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
DQ5  
A8  
+
+
+
*
*
*
Row Address Strobe  
Column Address Strobe  
Write Enable  
Output Enable  
Data In/Data Out  
Data In  
3
A9  
DQ1 +  
*
DQ2  
DQ3  
DQ4  
+
+
+
*
*
*
4
A10  
DQ6  
WE  
Vss  
DQ7  
NC  
5
A1  
OE  
OE  
Q
*
OE  
6
DQ2  
A2  
7
DQ1 - DQ8  
D9  
8
A3  
A0 - A9  
RAS  
CAS  
WE  
DQ1  
DQ2  
DQ3  
DQ4  
*
*
*
9
Vss  
DQ3  
A4  
10  
11  
12  
13  
14  
15  
DQ8  
NC  
Q9  
Data Out  
DQ5 +  
*
DQ6  
DQ7  
DQ8  
+
+
+
*
*
*
Vcc  
5v Supply  
A5  
RAS0  
NC  
*
DQ4  
A6  
Vss  
Ground  
NC  
NC  
No Connect  
A7  
Vcc  
A0 - A11  
RAS  
CAS  
*
*
PCAS  
+
MODULE OPTIONS  
* WE  
Leadless SIM: AK594096BS  
Leaded SIP: AK594096BG  
D9  
Q9  
+
+
D
*
*

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