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AHE2815DF/CH PDF预览

AHE2815DF/CH

更新时间: 2024-09-19 23:28:15
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其他 - ETC 转换器
页数 文件大小 规格书
8页 62K
描述
DC to DC Converter

AHE2815DF/CH 数据手册

 浏览型号AHE2815DF/CH的Datasheet PDF文件第2页浏览型号AHE2815DF/CH的Datasheet PDF文件第3页浏览型号AHE2815DF/CH的Datasheet PDF文件第4页浏览型号AHE2815DF/CH的Datasheet PDF文件第6页浏览型号AHE2815DF/CH的Datasheet PDF文件第7页浏览型号AHE2815DF/CH的Datasheet PDF文件第8页 
AHE28XXD Series  
AHE2815D  
Table II. Electrical Performance Characteristics - continued  
Test  
Symbol  
Conditions  
-55°C Tc +125°C  
Group A  
Subgroups  
Device  
Types  
Limits  
Unit  
Vin = 28 Vdc ±5%, CL = 0  
unless otherwise specified  
Min  
Max  
70  
Recovery time  
step transient  
load changes 1, 7  
TTLOAD  
50% load to/from 100% load  
4
All  
µs  
5,6  
100  
No load to 50% load  
50% load to no load  
Input step 17 to 40V dc  
4,5,6  
4,5,6  
4,5,6  
All  
All  
All  
1500  
5
1500  
ms  
mV pk  
Output response  
transient step  
VOTLINE  
line changes 5, 12  
Input step 40 to 17V dc  
Input step 17 to 40V dc  
4,5,6  
4,5,6  
All  
All  
-1500  
4
Recovery time  
transient  
TTLINE  
ms  
step line  
changes 1, 5, 12  
Input step 40 to 17V dc  
4,5,6  
4,5,6  
All  
All  
4
600  
Turn on  
VTonOS  
TonD  
TrLF  
mV pk  
ms  
IOUT = 0 and 500mA  
±
overshoot 9  
Turn on delay 2, 9  
4,5,6  
4,5,6  
All  
All  
10  
10  
IOUT = 0 and 500mA  
±
Load fault  
recovery 12  
ms  
Notes to Specifications  
1
2
3
Recovery time is measured from the initiation of the transient to where VOUT has returned to within ±.1 percent of VOUT at 50 percent  
load.  
Turn on delay time measurement is for either a step application of power at the input or the removal of a ground signal from the  
inhibit pin (pin 2) while power is applied to the input.  
An overload is that condition with a load in excess of the rated load but less than that necessary to trigger the short circuit  
protection and is the condition of maximum power dissipation.  
4
5
Total power at both outputs. For operation at 16 Vdc input, derate output power by 33 percent.  
Input step transition time between 2 and 10 microseconds.  
6 Capacitive load may be any value from 0 to the maximum limit without compromising dc performance. A capacitive load in excess  
of the maximum limit will not disturb loop stability but may interfere with the operation of the load fault detection circuitry, appearing  
as a short circuit during turn-on.  
7
8
9
Load step transition time between 2 and 10 microseconds.  
Bandwidth guaranteed by design. Tested for 20KHz to 2MHz.  
Tested at each output.  
10 When operating with unbalanced loads, at least 25 percent of the load must be on the positive output to maintain regulation.  
11 Parameter guaranteed by line and load regulation tests.  
12 Parameter shall be tested as part of design characterization and after design or process changes. Thereafter parameters shall be  
guaranteed to the limits specified in Table II.  
www.irf.com  
5

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