Datasheet > 可编程逻辑 > 现场可编程门阵列> AGLE3000V5-FFGG896C

AGLE3000V5-FFGG896C

更新时间： 2024-11-11 13:05:27

品牌	Logo	应用领域
ACTEL		现场可编程门阵列可编程逻辑栅时钟
页数	文件大小	规格书
156页	5023K
描述
Field Programmable Gate Array, 75264 CLBs, 3000000 Gates, CMOS, PBGA896, 31 X 31 MM, 2.23 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, FBGA-484

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AGLE3000V5-FFGG896C 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
包装说明：	31 X 31 MM, 2.23 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, FBGA-484	Reach Compliance Code：	compliant
风险等级：	5.78	JESD-30 代码：	S-PBGA-B896
JESD-609代码：	e1	长度：	31 mm
湿度敏感等级：	3	可配置逻辑块数量：	75264
等效关口数量：	3000000	端子数量：	896
最高工作温度：	70 °C	最低工作温度：
组织：	75264 CLBS, 3000000 GATES	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装形状：	SQUARE
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	250
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	2.44 mm	最大供电电压：	1.575 V
最小供电电压：	1.425 V	标称供电电压：	1.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN SILVER COPPER
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	40
宽度：	31 mm	Base Number Matches：	1

AGLE3000V5-FFGG896C 数据手册

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v1.2

IGLOOe Low-Power Flash FPGAs

with Flash*Freeze Technology

Pro (Professional) I/O

Features and Benefits

• 700 Mbps DDR, LVDS-Capable I/Os

Low Power

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—Up to 8 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and

LVCMOS 2.5 V / 5.0 V Input

• 1.2 V to 1.5 V Core Voltage Support for Low Power

• Supports Single-Voltage System Operation

• Low-Power Active FPGA Operation

• Flash*Freeze Technology Enables Ultra-Low Power

Consumption while Maintaining FPGA Content

• Flash*Freeze Pin Allows Easy Entry to / Exit from Ultra-Low-

Power Flash*Freeze Mode

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and

M-LVDS

• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL

2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3

Class I and II

High Capacity

• 600 k to 3 Million System Gates

• 108 to 504 kbits of True Dual-Port SRAM

• Up to 620 User I/Os

• I/O Registers on Input, Output, and Enable Paths

• Programmable Output Slew Rate and Drive Strength

• Programmable Input Delay

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

• Live-at-Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• Schmitt Trigger Option on Single-Ended Inputs

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the IGLOO e Family

• Retains Programmed Design when Powered Off

Clock Conditioning Circuit (CCC) and PLL

In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

• Six CCC Blocks, Each with an Integrated PLL

• Configurable Phase Shift, Multiply/Divide, Delay

Capabilities, and External Feedback

to Secure FPGA Contents

H^•igh^Fla-P^she^Lr^of^co^krmance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

• High-Performance, Low-Skew Global Network

• Architecture Supports Ultra-High Utilization

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

Embedded Memory

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

Blocks (×1, ×2, ×4, ×9, and ×18 organizations available)

A^•RM^TruP^er^Do^uc^ae^l-s^Ps^oo^rtr^SS^RAu^Mpp^(eo^xr^ct^epi^tn^×I¹G⁸⁾LOOe FPGAs

• M1 IGLOOe Devices—Cortex™-M1 Soft Processor Available

with or without Debug

IGLOOe Product Family

IGLOOe Devices

AGLE600

AGLE3000

ARM-Enabled IGLOOe Devices

System Gates

M1AGLE3000

600 k

13,824

3 M

75,264

137

504

112

1 k

VersaTiles (D-flip-flops)

Quiescent Current (typical) in Flash*Freeze Mode (µW)

RAM kbits (1,024 bits)

4,608-Bit Blocks

108

FlashROM Bits

1 k

Yes

Secure (AES) ISP

Yes

CCCs with Integrated PLLs

VersaNet Globals

I/O Banks

Maximum User I/Os

270

620

Package Pins

FBGA

FG256, FG484

FG484, FG896

Notes:

1. Refer to the Cortex-M1 Handbook for more information.

2. Six chip (main) and twelve quadrant global networks are available.

3. For devices supporting lower densities, refer to the IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology handbook.

October 2008

12 3 4 5 6 7...156

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与AGLE3000V5-FFGG896C相关器件

型号	品牌	获取价格	描述	数据表
AGLE3000V5-FFGG896ES	ACTEL	获取价格	IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE3000V5-FFGG896I	ACTEL	获取价格	IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE3000V5-FFGG896PP	ACTEL	获取价格	IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE3000V5-FG484I	MICROSEMI	获取价格	Field Programmable Gate Array, 75264 CLBs, 3000000 Gates, 250MHz, 75264-Cell, CMOS, PBGA48
AGLE3000V5-FG484Y	MICROSEMI	获取价格	Field Programmable Gate Array,
AGLE3000V5-FG484YC	MICROSEMI	获取价格	Field Programmable Gate Array
AGLE3000V5-FG484YI	MICROSEMI	获取价格	Field Programmable Gate Array,
AGLE3000V5-FG896	ACTEL	获取价格	IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE3000V5-FG896ES	ACTEL	获取价格	IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE3000V5-FG896I	ACTEL	获取价格	IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology

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