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AGLE3000V5-FFGG896I PDF预览

AGLE3000V5-FFGG896I

更新时间: 2024-11-11 06:36:43
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ACTEL /
页数 文件大小 规格书
156页 5023K
描述
IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology

AGLE3000V5-FFGG896I 数据手册

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v1.2  
®
IGLOOe Low-Power Flash FPGAs  
with Flash*Freeze Technology  
Pro (Professional) I/O  
Features and Benefits  
• 700 Mbps DDR, LVDS-Capable I/Os  
Low Power  
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation  
• Bank-Selectable I/O Voltages—Up to 8 Banks per Chip  
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /  
2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and  
LVCMOS 2.5 V / 5.0 V Input  
• 1.2 V to 1.5 V Core Voltage Support for Low Power  
• Supports Single-Voltage System Operation  
• Low-Power Active FPGA Operation  
• Flash*Freeze Technology Enables Ultra-Low Power  
Consumption while Maintaining FPGA Content  
• Flash*Freeze Pin Allows Easy Entry to / Exit from Ultra-Low-  
Power Flash*Freeze Mode  
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and  
M-LVDS  
• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL  
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3  
Class I and II  
High Capacity  
• 600 k to 3 Million System Gates  
• 108 to 504 kbits of True Dual-Port SRAM  
• Up to 620 User I/Os  
• I/O Registers on Input, Output, and Enable Paths  
• Programmable Output Slew Rate and Drive Strength  
• Programmable Input Delay  
Reprogrammable Flash Technology  
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process  
• Live-at-Power-Up (LAPU) Level 0 Support  
• Single-Chip Solution  
• Schmitt Trigger Option on Single-Ended Inputs  
• Weak Pull-Up/-Down  
• IEEE 1149.1 (JTAG) Boundary Scan Test  
®
• Pin-Compatible Packages across the IGLOO e Family  
• Retains Programmed Design when Powered Off  
Clock Conditioning Circuit (CCC) and PLL  
In-System Programming (ISP) and Security  
• Secure ISP Using On-Chip 128-Bit Advanced Encryption  
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)  
• Six CCC Blocks, Each with an Integrated PLL  
• Configurable Phase Shift, Multiply/Divide, Delay  
Capabilities, and External Feedback  
®
to Secure FPGA Contents  
HighFla-PsheLrofcokrmance Routing Hierarchy  
• Segmented, Hierarchical Routing and Clock Structure  
• High-Performance, Low-Skew Global Network  
• Architecture Supports Ultra-High Utilization  
• Wide Input Frequency Range (1.5 MHz up to 250 MHz)  
Embedded Memory  
• 1 kbit of FlashROM User Nonvolatile Memory  
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM  
Blocks (×1, ×2, ×4, ×9, and ×18 organizations available)  
ARMTruPerDoucael-sPsoortrSSRAuMpp(eoxrctepitn×I1G8)LOOe FPGAs  
• M1 IGLOOe Devices—Cortex™-M1 Soft Processor Available  
with or without Debug  
IGLOOe Product Family  
IGLOOe Devices  
AGLE600  
AGLE3000  
ARM-Enabled IGLOOe Devices  
System Gates  
M1AGLE3000  
600 k  
13,824  
49  
3 M  
75,264  
137  
504  
112  
1 k  
VersaTiles (D-flip-flops)  
Quiescent Current (typical) in Flash*Freeze Mode (µW)  
RAM kbits (1,024 bits)  
4,608-Bit Blocks  
108  
24  
FlashROM Bits  
1 k  
Yes  
6
Secure (AES) ISP  
Yes  
6
CCCs with Integrated PLLs  
1
VersaNet Globals  
18  
18  
I/O Banks  
8
8
Maximum User I/Os  
270  
620  
Package Pins  
FBGA  
FG256, FG484  
FG484, FG896  
Notes:  
1. Refer to the Cortex-M1 Handbook for more information.  
2. Six chip (main) and twelve quadrant global networks are available.  
3. For devices supporting lower densities, refer to the IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology handbook.  
October 2008  
I
© 2008 Actel Corporation  

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