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AFE1144 PDF预览

AFE1144

更新时间: 2024-10-27 22:05:27
品牌 Logo 应用领域
BB /
页数 文件大小 规格书
11页 116K
描述
HDSL/MDSL ANALOG FRONT END

AFE1144 数据手册

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compromise hybrid (rxHYB). The connection of these two  
inputs so that the hybrid signal is subtracted from the line  
signal is described in the paragraph titled “Echo Cancella-  
tion in the AFE”. The equivalent gain for each input in the  
difference amp is one. The resulting signal then passes to a  
programmable gain amplifier which can be set for gains of  
0dB through +12dB. Following the PGA, the ADC converts  
the signal to a 14-bit digital word.  
THEORY OF OPERATION  
The AFE1144 consists of a transmit and a receive channel.  
It interfaces to the HDSL DSP through a six wire serial  
interface, three wires for the transmit channel and three  
wires for the receive channel. It interfaces to the HDSL  
telephone line transformer and external compromise hybrid  
through transmit and receive analog connections.  
The transmit channel consists of a switched-capacitor pulse  
forming network followed by a differential line driver. The  
pulse forming network receives 2-bit digital symbol data and  
generates a filtered 2B1Q analog output waveform. The  
differential line driver uses a composite output stage com-  
bining class B operation (for high efficiency driving large  
signals) with class AB operation (to minimize crossover  
distortion).  
The serial interface consists of three wires for transmit and  
three wires for receive. The three wire transmit interface is  
transmit baud rate clock, transmit 48x oversampling clock  
and Data Out. The three wire receive interface is receive  
baud rate clock, receive 48x oversampling clock and Data  
In. The transmit and receive clocks are supplied to the  
AFE1144 from the DSP and are completely independent.  
The receive channel is designed around a fourth-order delta  
sigma A/D converter. It includes a difference amplifier  
designed to be used with an external compromise hybrid for  
first order analog echo cancellation. A programmable gain  
amplifier with gains of 0dB to +12dB is also included. The  
delta sigma modulator operating at a 24X oversampling ratio  
produces a 14-bit output at rates up to 584kHz (1.168Mbps).  
DIGITAL DATA INTERFACE  
Data is received by the AFE1144 from the DSP on the Data  
In line. Data is transmitted from the AFE1144 to the DSP on  
the Data Out line. The paragraphs below describe the timing  
of these signals and data structure.  
Data is transmitted and received in synchronization with the  
48x transmit and receive clocks (tx48xCLK and rx48xCLK).  
There are 48-bit times in each baud period. Data In is  
The receive channel operates by summing the two differen-  
tial inputs, one from the line (rxLINE) and the other from the  
rxbaudCLK  
rx48xCLK  
Data Out  
txbaudCLK  
tx48xCLK  
Data In  
HDSL  
DSP  
AFE1144  
FIGURE 1. DSP Interface.  
4ns  
4ns  
txbaudCLK  
from DSP  
A
B
4ns  
4ns  
tx48xCLK  
from DSP  
48  
1
2
3
4
15  
16  
47  
48  
1
Data In  
from DSP  
MSB  
Bit 15  
LSB  
Bit 0  
MSB  
Bit 15  
Transmit Timing Notes: (1) A baud period consists of 48 periods of the tx48xCLK. (2) The falling edge of the txbaudCLK  
can occur anywhere in area A. The rising edge can occur anywhere in area B. However, neither edge of the txbaudCLK  
can occur within 4ns (on either side) of any rising edge of tx48xCLK. (3) The AFE1144 reads Data In on the rising edge  
of the tx48xCLK. Data In must be stable at least 4ns before the rising edge of tx48xCLK and it must remain stable at  
least 4ns after the rising edge of tx48CLK. (4) Symbol data is transferred to the transmit pulse former after the LSB is  
read. The output analog symbol data reaches the peak of the symbol approximately 24 tx48xCLK periods later.  
FIGURE 2. Transmit Timing Diagram.  
®
AFE1144  
6

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