SHARC® Processor
ADSP-21375
a
Preliminary Technical Data
SUMMARY
High performance 32-bit/40-bit floating point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—0.5M bit of on-chip SRAM and a dedicated
2M bit of on-chip mask-programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21375 is available with a 266 MHz core instruction
rate with unique audio centric peripherals such as the digi-
tal applications interface, serial ports, precision clock
generators and more. For complete ordering information,
see Ordering Guide on Page 42
CORE PROCESSOR
4 BLOCKS OF
ON-CHIP MEMORY
INSTRUCTION
CACHE
TI MER
JTAG TEST & EMULATION
32 X 48-BIT
0.5M BIT RAM, 2M BIT ROM
DAG2
8X4X32
ADDR
32
DATA
64
DAG1
8X4X32
PROGRAM
SEQUENCER
FLAGS
4-15
16
EXTERNAL PORT
7
DATA
P M A D D RE SS BU S
DM ADDRES S BUS
32
SDRAM
CO NTRO LLE R
11
32
3
ASYNCHRONOUS
MEMO RY
INTERFACE
CONTROL
24
64
64
PM DATA BUS
IOA(24)
IOD(32)
ADDRESS
DM DATA BUS
DMA CONTROLLER
(24 CHANNELS)
PROCESSING
ELEMENT
(P EX)
PX REGISTER
PROCESSING
ELEMENT
(P EY)
IOP REGISTER (MEMORY MAPPED)
CONTROL, STATUS, & DATA BUFFERS
ME MO RY -TO-MEMORY
DMA (2)
SERIAL PORTS (4)
SPI PORT (2)
4
UART (1)
GPIO FLAGS/
IRQ/TIMEXP
INPUT DATA POR T/
PDAP
TWO WIRE
INTERFACE
PRECISION CLOCK
GENERATORS (4)
TIMERS (2)
DAI PINS
DPI PINS
S
DIGITAL PERIP HERAL INTE RFACE
DIGITAL APPLICATIONS INTERFACE
I/O PROCESSOR
14
20
Figure 1. Functional Block Diagram
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Rev. PrB
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