SHARC Processor
Preliminary Technical Data
ADSP-21462W/ADSP-21465W/ADSP-21467
Code compatible with all other members of the SHARC family
The ADSP-21462W/ADSP-21465W/ADSP-21467 are available
SUMMARY
Note: This datasheet is preliminary. This document contains
material that is subject to change without notice.
High performance 32-bit/40-bit floating point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
with unique audiocentric peripherals such as the digital
applications interface, DTCP (digital transmission content
protection protocol), serial ports, precision clock genera-
tors, S/PDIF transceiver, asynchronous sample rate
converters, input data port, and more.
For complete ordering information, see Automotive Prod-
ucts on Page 59 and Ordering Guide on Page 59.
On-chip memory—5 Mbits of on-chip RAM, 4 Mbits of on-chip
ROM
Automotive applications—the ADSP-21462W and the ADSP-
21465W are available exclusively as automotive products
CORE PROCESSOR
THERMAL
PLL
DIODE
4 BLOCKS OF
ON-CHIP MEMORY
INSTRUCTION
JTAGTEST & EMULATION
EXTERNAL PORT
CACHE
32 48-BIT
TIMER
x
5M BIT RAM
4M BIT ROM
DATA
8
FLAGS
PWM
DAG1
8 x 4 x 32
DAG2
8 x 4 x 32
ADDR
32
DATA
48
ASYNCHRONOUS
MEMORY
INTERFACE
(AMI)
PROGRAM
SEQUENCER
24 ADDRESS
3
7
AMI CONTROL
PM ADDRESS BUS
DMADDRESS BUS
32
32
DDR2 CONTROL
16
19
DDR2 DRAM
CONTROLLER
DATA
64
64
PM DATA BUS
DM DATA BUS
ADDRESS
IOA(19)
IOD(32)
ACCELERATORS
FFT FIR IIR
PX REGISTER
PROCESSING
ELEMENT
(PEX)
PROCESSING
ELEMENT
(PEY)
IOP REGISTER CONTROL
STATUS, & DATA BUFFERS
3/5
20
MLB
DMA
ARBITER
LINK
PORTS
4
GPIO
IRQ/FLAGS
SPI PORT (2)
SERIAL PORTS (8)
PRECISION CLOCK
GENERATORS (4)
TWOWIRE
INTERFACE
UART
DTCP
GP TIMERS (2)
INPUT DATA PORT/
PDAP
GPIO
S/PDIF (RX/TX)
ASRC
DPI PINS (14)
S
DAI PINS (20)
DIGITAL PERIPHERAL INTERFACE
I/O PROCESSOR
DIGITAL APPLICATIONS INTERFACE
20
14
Figure 1. Functional Block Diagram
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Rev. PrA
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