ADSP-21462W/ADSP-21465W/ADSP-21467
Preliminary Technical Data
GENERAL DESCRIPTION
The ADSP-21462W/ADSP-21465W/ADSP-21467 SHARC®
processors are members of the SIMD SHARC family of DSPs
that feature Analog Devices' Super Harvard Architecture. The
processors are source code compatible with the ADSP-2126x,
ADSP-2136x, ADSP-2137x, and ADSP-2116x DSPs as well as
with first generation ADSP-2106x SHARC processors in SISD
(single-instruction, single-data) mode. These new processors
are 32-bit/40-bit floating point processors optimized for high
performance audio applications with its large on-chip SRAM,
multiple internal buses to eliminate I/O bottlenecks, and an
innovative digital applications interface (DAI).
Table 1. SHARC Family Features (Continued)
Feature
AMI interface with 8-bit
support
Yes
Yes
Yes
SPI
2
2
2
TWI
Yes
Yes
Yes
Table 1. SHARC Family Features
Package
324-ball
PBGA
324-ball
PBGA
324-ball
PBGA
SRC Performance
128 dB
128 dB
128 dB
1 Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Prologic IIx,
DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like bass
management, delay, speaker equalization, graphic equalization, and more.
Decoder/post-processor algorithm combination support varies depending
upon the chip version and the system configurations. Please visit
www.analog.com for complete information.
Feature
Frequency
400 MHz 400 MHz 450 MHz
RAM
ROM1
5M bits
4M bits
No
5M bits
4M bits
Yes
5M bits
4M bits
Yes
2 The ADSP-21462W and ADSP-21465W processors provide the Digital Trans-
mission Content Protection protocol, a proprietary security protocol. Contact
your Analog Devices sales office for more information.
Audio Decoders in ROM
Pulse-Width Modulation
S/PDIF
As shown in the functional block diagram on Page 1, the
processor uses two computational units to deliver a significant
performance increase over the previous SHARC processors on a
range of DSP algorithms. Fabricated in a state-of-the-art, high
speed, CMOS process, the processor achieves an instruction
cycle time of 2.22 ns at 450 MHz (ADSP-21467) and 2.5 ns at
400 MHz (ADSP-21462W, ADSP-21465W). With its SIMD
computational hardware, the processors can perform 2.7
GFLOPS running at 450 MHz (ADSP-21467) and 2.4 GFLOPS
running at 400 MHz (ADSP-21462W, ADSP-21465W).
Yes
Yes
Yes
Yes
Yes
Yes
DTCP2
Yes
Yes
No
DDR2 Memory Interface
1/2 CCLK 1/2 CCLK 1/2 CCLK
Max
Max
Max
DDR2 Memory Bus Width 16 bits
16 bits
Yes
16 bits
Yes
Direct DMA from SPORTs
to external memory
Yes
Table 2 shows performance benchmarks for the ADSP-2146x
processors.
FIR accelerator
IIR accelerator
FFT accelerator
MLB Interface
IDP
Yes
Yes
Yes
Yes
Yes
8
Yes
Yes
Yes
Yes
Yes
8
Yes
Yes
Yes
No
Yes
8
Table 2. Processor Benchmarks
Speed
(at 450 MHz)
Benchmark Algorithm
1024 Point Complex FFT (Radix 4, With Reversal) 20.44 μs
Serial Ports
SRU
FIR Filter (per Tap)1
IIR Filter (per Biquad)1
1.11 ns
4.43 ns
2
2
2
Matrix Multiply (Pipelined)
[3 × 3] × [3 × 1]
[4 × 4] × [4 × 1]
DDR2 Memory Interface
UART
Yes
1
Yes
1
Yes
1
10.0 ns
17.78 ns
DAI and DPI
20/14
pins
20/14
pins
20/14
pins
Divide (y/×)
6.67 ns
10.0 ns
Inverse Square Root
1 Assumes two files in multichannel SIMD mode
Link ports
2
1
2
1
2
1
S/PDIF transceiver
Rev. PrA
|
Page 4 of 60
|
November 2008
5秒后页面跳转
深入解析AD7606高性能多通道模数转换器：资料手册参数分析
74HC573三态非易失锁存器(Latch)资料手册参数分析
MAX3232 RS-232电平转换器资料手册参数分析
MAX485 RS-485/RS-422收发器资料手册参数分析
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
