Datasheet > 微控制器和处理器 > 数字信号处理器> ADSP-21369BBP-2A

ADSP-21369BBP-2A

更新时间： 2024-01-25 03:57:24

品牌	Logo	应用领域
亚德诺 - ADI		微控制器和处理器外围集成电路数字信号处理器时钟
页数	文件大小	规格书
56页	1696K
描述
SHARC Processors

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技术参数
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ADSP-21369BBP-2A 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	BGA
包装说明：	LBGA,	针数：	256
Reach Compliance Code：	unknown	风险等级：	5.72
其他特性：	ALSO REQUIRES 3.3V SUPPLY	地址总线宽度：	24
桶式移位器：	YES	边界扫描：	YES
最大时钟频率：	55.56 MHz	外部数据总线宽度：	32
格式：	FLOATING POINT	内部总线架构：	MULTIPLE
JESD-30 代码：	S-PBGA-B256	JESD-609代码：	e0
长度：	27 mm	低功率模式：	NO
湿度敏感等级：	3	端子数量：	256
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装形状：	SQUARE	封装形式：	GRID ARRAY, LOW PROFILE
峰值回流温度（摄氏度）：	225	认证状态：	COMMERCIAL
座面最大高度：	1.7 mm	最大供电电压：	1.26 V
最小供电电压：	1.14 V	标称供电电压：	1.2 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	TIN LEAD
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	30
宽度：	27 mm	uPs/uCs/外围集成电路类型：	DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：	1

ADSP-21369BBP-2A 数据手册

浏览型号ADSP-21369BBP-2A的Datasheet PDF文件第11页

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ADSP-21367/ADSP-21368/ADSP-21369

developer can identify bottlenecks in software quickly and effi-

ciently. By using the profiler, the programmer can focus on

those areas in the program that impact performance and take

corrective action.

ADSP-213xx

100nF

10nF

1nF

VDD

DDINT

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

HI-Z FERRITE

BEAD CHIP

VSS

• View mixed C/C++ and assembly code (interleaved source

and object information)

LOCATE ALL COMPONENTS

CLOSE TO A AND A PINS

VDD

VSS

• Insert breakpoints

• Set conditional breakpoints on registers, memory,

and stacks

Figure 2. Analog Power (A_VDD) Filter Circuit

• Trace instruction execution

Target Board JTAG Emulator Connector

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

Analog Devices DSP Tools product line of JTAG emulators uses

the IEEE 1149.1 JTAG test access port of the ADSP-21367/

ADSP-21368/ADSP-21369 processors to monitor and control

the target board processor during emulation. Analog Devices

DSP Tools product line of JTAG emulators provides emulation

at full processor speed, allowing inspection and modification of

memory, registers, and processor stacks. The processor’s JTAG

interface ensures that the emulator will not affect target system

loading or timing.

• Create custom debugger windows

The VisualDSP++ IDDE lets programmers define and manage

DSP software development. Its dialog boxes and property pages

let programmers configure and manage all of the SHARC devel-

opment tools, including the color syntax highlighting in the

VisualDSP++ editor. This capability permits programmers to:

For complete information on Analog Devices’ SHARC DSP

Tools product line of JTAG emulator operation, see the appro-

priate “Emulator Hardware User’s Guide.”

• Control how the development tools process inputs and

generate outputs

• Maintain a one-to-one correspondence with the tool’s

command line switches

DEVELOPMENT TOOLS

The processors are supported with a complete set of CROSS-

The VisualDSP++ Kernel (VDK) incorporates scheduling and

resource management tailored specifically to address the mem-

ory and timing constraints of DSP programming. These

capabilities enable engineers to develop code more effectively,

eliminating the need to start from the very beginning, when

developing new application code. The VDK features include

threads, critical and unscheduled regions, semaphores, events,

and device flags. The VDK also supports priority-based, pre-

emptive, cooperative, and time-sliced scheduling approaches. In

addition, the VDK was designed to be scalable. If the application

does not use a specific feature, the support code for that feature

is excluded from the target system.

CORE software and hardware development tools, including

Analog Devices emulators and VisualDSP++ development

environment. The same emulator hardware that supports other

SHARC processors also fully emulates the ADSP-21367/ADSP-

21368/ADSP-21369.

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy to use assembler (which is based on an alge-

braic syntax), an archiver (librarian/library builder), a linker, a

loader, a cycle-accurate instruction-level simulator, a C/C++

compiler, and a C/C++ runtime library that includes DSP and

mathematical functions. A key point for these tools is C/C++

code efficiency. The compiler has been developed for efficient

translation of C/C++ code to DSP assembly. The SHARC has

architectural features that improve the efficiency of compiled

C/C++ code.

Because the VDK is a library, a developer can decide whether to

use it or not. The VDK is integrated into the VisualDSP++

development environment, but can also be used via standard

command line tools. When the VDK is used, the development

environment assists the developer with many error-prone tasks

and assists in managing system resources, automating the gen-

eration of various VDK-based objects, and visualizing the

system state, when debugging an application that uses the VDK.

The VisualDSP++ debugger has a number of important fea-

tures. Data visualization is enhanced by a plotting package that

offers a significant level of flexibility. This graphical representa-

tion of user data enables the programmer to quickly determine

the performance of an algorithm. As algorithms grow in com-

plexity, this capability can have increasing significance on the

designer’s development schedule, increasing productivity. Sta-

tistical profiling enables the programmer to nonintrusively poll

the processor as it is running the program. This feature, unique

to VisualDSP++, enables the software developer to passively

gather important code execution metrics without interrupting

the real-time characteristics of the program. Essentially, the

VisualDSP++ Component Software Engineering (VCSE) is

Analog Devices’ technology for creating, using, and reusing

software components (independent modules of substantial

functionality) to quickly and reliably assemble software

applications. The user can download components from the

Web, drop them into the application, and publish component

archives from within VisualDSP++. VCSE supports component

implementation in C/C++ or assembly language.

Rev. A

Page 10 of 56

August 2006

1...7 8 91011 12 13...56

中文翻译

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ADSP-21369BBP-2A 替代型号

型号	品牌	替代类型	描述	数据表
ADSP-21369BBPZ-2A	ADI	完全替代	SHARC Processors
ADSP-21369KBPZ-2A	ADI	类似代替	SHARC Processors
ADSP-21369KBP-2A	ADI	类似代替	SHARC Processors

与ADSP-21369BBP-2A相关器件

型号	品牌	获取价格	描述	数据表
ADSP-21369BBPZ-2A	ADI	获取价格	SHARC Processors
ADSP-21369BSWZ-1A	ADI	获取价格	SHARC Processors
ADSP-21369BSWZ-2A	ADI	获取价格	SHARC Processors
ADSP-21369KBP-2A	ADI	获取价格	SHARC Processors
ADSP-21369KBP-3A	ADI	获取价格	IC 0-BIT, 25 MHz, OTHER DSP, PBGA256, SBGA-256, Digital Signal Processor
ADSP-21369KBP-ENG	ADI	获取价格	IC 32-BIT, 66.66 MHz, OTHER DSP, PBGA256, MO-192-BAL-2, SBGA-256, Digital Signal Processor
ADSP-21369KBPZ-2A	ADI	获取价格	SHARC Processors
ADSP-21369KBPZ-3A	ADI	获取价格	SHARC Processors
ADSP-21369KBPZ-ENG	ADI	获取价格	IC 32-BIT, 66.66 MHz, OTHER DSP, PBGA256, LEAD FREE, MO-192-BAL-2, SBGA-256, Digital Signa
ADSP-21369KBPZ-X	ADI	获取价格	IC 32-BIT, 55.55 MHz, OTHER DSP, PBGA256, LEAD FREE, MO-192BAL-2, SBGA-256, Digital Signal

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