SHARC® Processor
ADSP-21369
a
Preliminary Technical Data
SUMMARY
The ADSP-21369 is available with a 400 MHz core instruction
rate with unique audio centric peripherals such as the Digi-
tal Audio Interface, S/PDIF transceiver, serial ports, 8-
channel asynchronous sample rate converter, precision
clock generators and more. For complete ordering infor-
mation, see Ordering Guide on Page 52
High performance 32-bit/40-bit floating point processor
optimized for high performance audio processing
Single-Instruction Multiple-Data (SIMD) computational
architecture
On-chip memory—2M bit of on-chip SRAM and 6M bit of on-
chip mask programmable ROM
Code compatible with all other members of the SHARC family
CORE PROCESSOR
INSTRUCTION
4 BLOCKS OF
ON-CHIP MEMORY
JTAG TEST & EMULATION
CACHE
TI MER
32 X 48-BI T
2M BIT RAM,
6M BIT ROM (*Reserved)
FLAGS
4-15
DAG2
8X4X32
DAG1
8X4X32
PROGRAM
SEQUENCER
ADDR
DATA
PWM
32
EXTERNAL PORT
DATA
8
P M ADDRE SS BUS
DM ADDRES S BUS
32
SDRAM
CONTROLLER
11
32
3
ASYNCHRONOUS
MEMO RY
INTERFACE
CONTROL
24
64
64
PM DATA BUS
IOA(24)
IOD(32)
ADDRESS
DM DATA BUS
DMA
CONTROLLER
PROCESSING
ELEMENT
(P EX)
PX REGISTER
PROCESSING
ELEMENT
(P EY)
IOP REGISTER (MEMORY MAPPED)
CONTROL, STATUS, & DATA BUFFERS
34 CHANNE LS
MEMORY-TO-
MEMORY DMA (2)
PRECISION CLOCK
GENERATORS (4)
SERIAL PORTS (8)
SPI PORT (2)
4
UART (2)
GPIO FLAGS/
INPUT DATA PORT/
PDAP
IRQ/TIMEXP
TWO WIRE
INTERFACE
SRC (8 CHANNELS)
SPDIF (RX/TX)
TIMERS (3)
DAI PINS
DPI PINS
S
DIGITAL PERIP HERAL INTE RFACE
DIGITAL AUDIO INTERFACE
I/O PROCESSOR
14
20
*THE ADSP-21369 PROCESSOR INCLUDES A CUSTOMER-DEFINABLE ROM BLOCK.
PLEASE CONTACT YOUR ANALOG DEVICES SALE S REPRESENTATIVE FOR ADDITIONAL DETAILS
Figure 1. Functional Block Diagram
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Rev. PrB
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