SHARC Processor
ADSP-21371/ADSP-21375
SUMMARY
DEDICATED AUDIO COMPONENTS
High performance 32-bit/40-bit floating point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory, ADSP-21371—1M bits of on-chip SRAM
and 4M bits of on-chip mask-programmable ROM
On-chip memory, ADSP-21375—0.5M bits of on-chip
SRAM and 2M bits of on-chip mask-programmable ROM
ADSP-21371—S/PDIF-compatible digital audio
receiver/transmitter
ADSP-21371—8 dual data line serial ports that operate at up
to 50 Mbps on each data line — each has a clock, frame
sync, and two data lines that can be configured as either a
receiver or transmitter pair
16 PWM outputs configured as four groups of four outputs
ROM-based security features include
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
access under program control to sensitive code
PLL has a wide variety of software and hardware multi-
plier/divider ratios
Code compatible with all other members of the SHARC family
The ADSP-21371/ADSP-21375 processors are available with a
200/266 MHz core instruction rate with unique audiocen-
tric peripherals such as the digital applications interface,
S/PDIF transceiver, serial ports, precision clock generators,
and more. For complete ordering information, see Order-
ing Guide on Page 52.
Available in a 208-lead LQFP_EP package
Internal Memory
SIMD Core
Block 0
RAM/ROM
Block 1
RAM/ROM
Block 2
RAM
Block 3
RAM
Instruction
Cache
5 stage
Sequencer
B2D
64-BIT
B0D
64-BIT
B3D
64-BIT
B1D
64-BIT
S
DAG1/2
PEx
Timer
PEy
DMD 64-BIT
PMD 64-BIT
DMD 64-BIT
Core Bus
Cross Bar
Internal Memory I/F
PMD 64-BIT
IODO 32-BIT
FLAGx/IRQx/
TMREXP
EPD BUS 48-BIT
JTAG
PERIPHERAL BUS
32-BIT
IOD1
32-BIT
IOD0 BUS
MTM/
DTCP
PERIPHERAL BUS
EP
IDP/
PDAP
7-0
S/PDIF
Tx/Rx
CORE PCG
FLAGS
TIMER
PCG
SPORT
CORE PWM
AMI
TWI
SPI/B
UART
SDRAM
C
-
D
1-0
A
-
D
7-0
FLAGS
3-0
DPI Routing/Pins
External Port Pin MUX
DAI Routing/Pins
External
Port
DPI Peripherals
DAI Peripherals
Peripherals
Figure 1. Functional Block Diagram
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Rev. C
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