ADSP-21364
by the boot configuration (BOOTCFG1–0) pins (see Table 6 on
Page 14). Selection of the boot source is controlled via the SPI as
either a master or slave device.
For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, see the appro-
priate “Emulator Hardware User's Guide”.
Phase-Locked Loop
DEVELOPMENT TOOLS
The ADSP-21364 uses an on-chip phase-locked loop (PLL) to
generate the internal clock for the core. On power up, the
CLKCFG1–0 pins are used to select ratios of 32:1, 16:1, and 6:1
(see Table 7 on Page 14). After booting, numerous other ratios
can be selected via software control. The ratios are made up of
software configurable numerator values from 1 to 64 and soft-
ware configurable divisor values of 1, 2, 4, and 8.
The ADSP-21364 is supported with a complete set of
CROSSCORE® software and hardware development tools,
including Analog Devices emulators and VisualDSP++® devel-
opment environment. The same emulator hardware that
supports other SHARC processors also fully emulates the
ADSP-21364.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge-
braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ run-time library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The SHARC has
architectural features that improve the efficiency of compiled
C/C++ code.
Power Supplies
The ADSP-21364 has separate power supply connections for the
internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS
)
power supplies. The internal and analog supplies must meet the
1.2 V requirement for K and B grade models, and the 1.0 V
requirement for W grade models. The external supply must
meet the 3.3 V requirement. All external supply pins must be
connected to the same power supply.
Note that the analog supply pin (AVDD) powers the ADSP-
21364’s internal clock generator PLL. To produce a stable clock,
it is recommended that PCB designs use an external filter circuit
for the AVDD pin. Place the filter components as close as possi-
ble to the AVDD/AVSS pins. For an example circuit, see Figure 4.
(A recommended ferrite chip is the muRata
The VisualDSP++ debugger has a number of important fea-
tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa-
tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com-
plexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Sta-
tistical profiling enables the programmer to nonintrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and effi-
ciently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.
BLM18AG102SN1D). To reduce noise coupling, the PCB
should use a parallel pair of power and ground planes for
VDDINT and GND. Use wide traces to connect the bypass capac-
itors to the analog power (AVDD) and ground (AVSS) pins. Note
that the AVDD and AVSS pins specified in Figure 4 are inputs to
the processor and not the analog ground plane on the board—
the AVSS pin should connect directly to digital ground (GND) at
the chip.
ADSP-213xx
100nF
10nF
1nF
A
V
VDD
DDINT
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
HI Z FERRITE
BEAD CHIP
• View mixed C/C++ and assembly code (interleaved source
and object information)
A
VSS
• Insert breakpoints
LOCATE ALL COMPONENTS
CLOSE TO A AND A PINS
VDD
VSS
• Set conditional breakpoints on registers, memory,
and stacks
Figure 4. Analog Power (AVDD) Filter Circuit
• Trace instruction execution
• Perform linear or statistical profiling of program execution
• Fill, dump, and graphically plot the contents of memory
• Perform source level debugging
Target Board JTAG Emulator Connector
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-21364 pro-
cessor to monitor and control the target board processor during
emulation. Analog Devices DSP Tools product line of JTAG
emulators provides emulation at full processor speed, allowing
inspection and modification of memory, registers, and proces-
sor stacks. The processor's JTAG interface ensures that the
emulator will not affect target system loading or timing.
• Create custom debugger windows
Rev. 0
|
Page 9 of 56
|
October 2005
5秒后页面跳转
压敏电阻器在直流电路中的过压保护应用探讨
电感耐压值及其与电感大小的关系
CNY17F光耦合器：特性、应用、封装、引脚功能及替换型号解析
DS1307资料解析：特性、引脚说明、替代推荐
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
技术参数
数据手册
如果您发现信息不准确，
