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ADSP-21364SKSQ-ENG PDF预览

ADSP-21364SKSQ-ENG

更新时间: 2024-11-20 22:16:43
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
52页 487K
描述
SHARC Processor

ADSP-21364SKSQ-ENG 数据手册

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SHARC® Processor  
ADSP-21364  
a
Preliminary Technical Data  
SUMMARY  
On-chip memory—3M bit of on-chip SRAM and a dedicated  
4M bit of on-chip mask-programmable ROM  
High performance 32-bit/40-bit floating point processor  
optimized for professional audio processing  
Code compatible with all other members of the SHARC family  
The ADSP-21364 is available with a 333 MHz core instruction  
rate and unique audio centric peripherals such as the Digi-  
tal Audio Interface, S/PDIF transceiver, serial ports, 8-  
channel asynchronous sample rate converter, precision  
clock generators and more. For complete ordering infor-  
mation, see Ordering Guide on Page 52  
At 333 MHz/2 GFLOPs, with unique audio centric peripherals  
such as the Digital Audio Interface that includes a high-  
precision 8-channel asynchronous sample rate converter  
among others, the ADSP-21364 SHARC processor is ideal  
for applications that require industry leading equalization,  
reverberation and other effects processing  
Single-Instruction Multiple-Data (SIMD) computational  
architecture  
Two 32-bit IEEE floating-point/32-bit fixed-point/40-bit  
extended precision floating-point computational units,  
each with a multiplier, ALU, shifter, and register file  
4 BLOCKS OF ON-CHIP MEMORY  
CORE PROCESSOR  
INSTRUCTION  
BLOCK 0  
SRAM  
1M BIT ROM  
2M BIT  
BLOCK 1  
BLOCK 2  
BLOCK 3  
SRAM  
1M BIT  
CACHE  
TIMER  
SRAM  
0.5M BIT  
SRAM  
0.5M BIT  
ROM  
2M BIT  
32 X 48-BIT  
ADDR  
DATA  
ADDR  
DATA  
ADDR  
DATA  
ADDR  
DATA  
DAG1  
8X4X32  
DAG2  
8X4X32  
PROGRAM  
SEQUENCER  
32  
PM ADDRESS BUS  
32  
64  
DM ADDRESS BUS  
PM DATA BUS  
64  
DM DATA BUS  
IOA  
IOD  
IOA  
IOD  
IOA  
IOD  
IOA  
IOD  
PX REGISTER  
SPI  
SPORTS  
IDP  
PCG  
TIMERS  
SRC  
PROCESSING  
ELEMENT  
(PEX)  
PROCESSING  
ELEMENT  
(PEY)  
IOP REGISTERS  
(MEMORY MAPPED)  
SIGNAL  
ROUTING  
UNIT  
SPDIF  
6
JTAG TEST & EMULATION  
I/O PROCESSOR  
AND PERIPHERALS  
SEE “ADSP-21364 MEMORY  
AND I/O INTERFACE FEATURES”  
SECTION FOR DETAILS  
S
Figure 1. Functional Block Diagram – Processor Core  
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.  
Rev. PrB  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective companies.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.  
Tel:781.329.4700  
Fax:781.326.8703  
www.analog.com  
© 2004 Analog Devices, Inc. All rights reserved.  

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