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ADSP-21365BSQZ-1AA

更新时间： 2024-11-22 03:10:19
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
56页 2873K
描述
IC 16-BIT, 55.55 MHz, OTHER DSP, PQFP144, LEAD FREE, MS-026BFB-HD, LQFP-144, Digital Signal Processor

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SHARC® Processor  
ADSP-21365  
a
Single-instruction, multiple-data (SIMD) computational  
architecture  
On-chip memory—3M bit of on-chip SRAM and a dedicated  
4M bit of on-chip mask-programmable ROM  
SUMMARY  
High performance 32-bit/40-bit floating-point processor  
optimized for high performance automotive audio  
processing  
Code compatible with all other members of the SHARC family  
The ADSP-21365 is available with a 333 MHz core instruction  
rate and unique audiocentric peripherals such as the digi-  
tal audio interface, S/PDIF transceiver, DTCP (digital  
transmission content protocol), serial ports, 8-channel  
asynchronous sample rate converter, precision clock gen-  
erators and more. For complete ordering information, see  
Ordering Guide 53.  
Audio decoder and post processor-algorithm support with  
32-bit floating-point implementations  
Nonvolatile memory may be configured to support audio  
decoders and post processor-algorithms like PCM, Dolby®  
Digital EX, Dolby Prologic IIx, DTS 96/24, Neo:6, DTS ESTM,  
MPEG2 AAC, MPEG2 2-channel, MP3, and functions like  
bass management, delay, speaker equalization, graphic  
equalization, and more. Decoder/post-processor algo-  
rithm combination support will vary depending upon the  
chip version and the system configurations. Please visit  
www.analog.com/SHARC.  
4 BLOCKS OF ON-CHIP MEMORY  
CORE PROCESSOR  
INSTRUCTION  
BLOCK 0  
SRAM  
BLOCK 1  
BLOCK 2  
BLOCK 3  
SRAM  
1M BIT  
CACHE  
TIMER  
SRAM  
0.5M BIT  
SRAM  
0.5M BIT  
1M BIT ROM  
ROM  
2M BIT  
32 X 48-BIT  
2M BIT  
ADDR  
DATA  
ADDR  
DATA  
ADDR  
DATA  
ADDR  
DATA  
DAG1  
8X4X32  
DAG2  
8X4X32  
PROGRAM  
SEQUENCER  
32  
PM ADDRESS BUS  
32  
64  
DM ADDRESS BUS  
PM DATA BUS  
64  
DM DATA BUS  
IOA  
IOD  
IOA  
IOD  
IOA  
IOD  
IOA  
IOD  
PX REGISTER  
SPI  
SPORTS  
IDP  
PCG  
TIMERS  
SRC  
PROCESSING  
ELEMENT  
(PEX)  
PROCESSING  
ELEMENT  
(PEY)  
IOP REGISTERS  
(MEMORY MAPPED)  
SIGNAL  
ROUTING  
UNIT  
SPDIF  
DTCP  
6
JTAG TEST AND EMULATION  
I/O PROCESSOR  
AND PERIPHERALS  
SEE ADSP-21365 MEMORY  
AND I/O INTERFACE FEATURES  
SECTION FOR DETAILS  
S
Figure 1. Functional Block Diagram—Processor Core  
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.3113  
www.analog.com  
© 2005 Analog Devices, Inc. All rights reserved.  
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