SHARC Processors
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
SUMMARY
DEDICATED AUDIO COMPONENTS
High performance 32-bit/40-bit floating point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
S/PDIF-compatible digital audio receiver/transmitter
8 channels of asynchronous sample rate converters (SRC)
16 PWM outputs configured as four groups of four outputs
ROM-based security features include:
On-chip memory—3M bits of on-chip SRAM
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
access under program control to sensitive code
PLL has a wide variety of software and hardware multi-
plier/divider ratios
Code compatible with all other members of the SHARC family
The ADSP-2136x processors are available with up to 333 MHz
core instruction rate with unique audiocentric peripherals
such as the digital applications interface, S/PDIF trans-
ceiver, DTCP (digital transmission content protection
protocol), serial ports, precision clock generators, and
more. For complete ordering information, see Ordering
Guide on Page 56.
Available in 136-ball CSP_BGA and 144-lead LQFP_EP
packages
Internal Memory
SIMD Core
Block 0
RAM/ROM
Block 1
RAM/ROM
Block 2
RAM
Block 3
RAM
Instruction
Cache
5 stage
Sequencer
B2D
64-BIT
B0D
64-BIT
B3D
64-BIT
B1D
64-BIT
S
DAG1/2
PEx
Timer
PEy
DMD 64-BIT
PMD 64-BIT
DMD 64-BIT
PMD 64-BIT
Core Bus
Cross Bar
Internal Memory I/F
FLAGx/IRQx/
TMREXP
JTAG
PERIPHERAL BUS
32-BIT
IOD 32-BIT
MTM/
DTCP
IOD BUS
PERIPHERAL BUS
CORE TIMER ASRC S/PDIF PCG
FLAGS Tx/Rx
Core
Flags
PDAP/ SPORT
IDP7-0
PWM
3-0
SPI B
PP
SPI
2
-
0
3-0
A-B
5
-
0
DAI Routing/Pins
PP Pin MUX
DAI Peripherals
Peripherals
Figure 1. Functional Block Diagram
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