SHARC Processors
ADSP-21367/ADSP-21368/ADSP-21369
The ADSP-21367/ADSP-21368/ADSP-21369 are available
with a 400 MHz core instruction rate with unique audiocen-
tric peripherals such as the digital audio interface, S/PDIF
transceiver, serial ports, 8-channel asynchronous sample
rate converter, precision clock generators, and more. For
complete ordering information, see Ordering Guide on
Page 55.
SUMMARY
High performance 32-bit/40-bit floating-point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—2M bits of on-chip SRAM and 6M bits of
on-chip mask programmable ROM
Code compatible with all other members of the SHARC family
JTAG TEST & EMULATION
CORE PROCESSOR
INSTRUCTION
4 BLOCKS OF
ON-CHIP MEMORY
CACHE
TIMERS
FLAGS4-15
PWM
32ꢀu 48-BIT
2M BIT RAM
6M BIT ROM
32
DAG2
8 u 4 u 32
DAG1
8 u 4 u 32
PROGRAM
SEQUENCER
ADDR
DATA
EXTERNAL PORT
DATA
7
SDRAM
CONTROLLER
18
3
PM ADDRESS BUS
DM ADDRESS BUS
32
32
ASYNCHRONOUS
MEMORY INTERFACE
CONTROL
24
8
64
64
PM DATA BUS
SHARED MEMORY
INTERFACE
ADDRESS
DM DATA BUS
IOA(24)
IOD(32)
DMA
CONTROLLER
PX REGISTER
IOP REGISTER (MEMORY MAPPED)
CONTROL, STATUS, AND DATA BUFFERS
PROCESSING
ELEMENT
(PEY)
PROCESSING
ELEMENT
(PEX)
34 CHANNELS
MEMORY-TO-
MEMORY DMA (2)
PRECISION CLOCK
GENERATORS (4)
SERIAL PORTS (8)
SPI PORT (2)
4
UART (2)
GPIO FLAGS/
IRQ/TIMEXP
INPUT DATA PORT/
PDAP
2-WIRE
INTERFACE
SRC (8 CHANNELS)
SPDIF (Rx/Tx)
TIMERS (3)
DAI PINS
DPI PINS
S
DIGITAL PERIPHERAL INTERFACE
I/O PROCESSOR
DIGITAL AUDIO INTERFACE
20
14
Figure 1. Functional Block Diagram
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Rev. C
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