ADSP-21367/ADSP-21368/ADSP-21369
Digital peripheral interface (DPI) includes three timers, two
UARTs, two SPI ports, and a 2-wire interface port
Outputs of PCG's C and D can be driven on to DPI pins
8 dual data line serial ports that operate at up to
50 Mbps on each data line—each has a clock, frame sync,
and two data lines that can be configured as either a
receiver or transmitter pair
TDM support for telecommunications interfaces including
128 TDM channel support for newer telephony interfaces
such as H.100/H.110
Up to 16 TDM stream support, each with 128 channels per
frame
Companding selection on a per channel basis in TDM mode
Input data port, configurable as eight channels of serial data
or seven channels of serial data and up to a 20-bit wide
parallel data channel
KEY FEATURES—PROCESSOR CORE
At 400 MHz (2.5 ns) core instruction rate, the processors per-
form 2.4G FLOPS/800 MMACS
2M bit on-chip, SRAM (0.75M bit in blocks 0 and 1, and
0.25M bit in blocks 2 and 3) for simultaneous access by the
core processor and DMA
6M bit on-chip, mask-programmable ROM (3M bit in block 0
and 3M bit in block 1)
Dual data address generators (DAGs) with modulo and bit-
reverse addressing
Zero-overhead looping with single-cycle loop setup, provid-
ing efficient program sequencing
Single-instruction, multiple-data (SIMD) architecture
provides:
Two computational processing elements
Concurrent execution
Code compatibility with other SHARC family members at
the assembly level
Signal routing unit provides configurable and flexible con-
nections between all DAI/DPI components
2 muxed flag/IRQ lines
1 muxed flag/timer expired line /MS pin
1 muxed flag/IRQ /MS pin
Parallelism in buses and computational units allows:
single-cycle executions (with or without SIMD) of a mul-
tiply operation, an ALU operation, a dual memory read
or write, and an instruction fetch
Transfers between memory and core at a sustained
6.4 Gbps bandwidth at 400 MHz core instruction rate
DEDICATED AUDIO COMPONENTS
S/PDIF-compatible digital audio receiver/transmitter sup-
ports EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards
Left-justified, I2S, or right-justified serial data input with
16-, 18-, 20- or 24-bit word widths (transmitter)
4 independent asynchronous sample rate converters (SRC).
Each converter has separate serial input and output ports,
a de-emphasis filter providing up to –140 dB SNR perfor-
mance, stereo sample rate converter and supports left-
justified, I2S, TDM, and right-justified modes and 24-, 20-,
18-, and 16-audio data word lengths
INPUT/OUTPUT FEATURES
DMA controller supports:
34 zero-overhead DMA channels for transfers between
internal memory and a variety of peripherals
32-bit DMA transfers at peripheral clock speed, in parallel
with full-speed processor execution
32-bit wide external port provides glueless connection to
both synchronous (SDRAM) and asynchronous memory
devices
Programmable wait state options: 2 SCLK to 31 SCLK cycles
Delay-line DMA engine maintains circular buffers in exter-
nal memory with tap-/offset-based reads
SDRAM accesses at 166 MHz and asynchronous accesses at
55 MHz
Shared-memory support allows multiple DSPs to automat-
ically arbitrate for the bus and gluelessly access a
common memory device
Pulse-width modulation provides:
16 PWM outputs configured as four groups of four outputs
supports center-aligned or edge-aligned PWM waveforms
ROM-based security features include:
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
access under program control to sensitive code
PLL has a wide variety of software and hardware multi-
plier/divider ratios
Dual voltage: 3.3 V I/O, 1.2 V or 1.3 V core
Available in 256-ball BGA_ED and 208-lead LQFP_EP pack-
ages (see Ordering Guide on Page 55)
Shared memory interface (ADSP-21368 only) support
provides:
Glueless connection for scalable DSP multiprocessing
architecture
Distributed on-chip bus arbitration for parallel bus
Connect of up to four ADSP-21368 processors and global
memory
Four memory select lines allow multiple external memory
devices
Digital audio interface (DAI) includes eight serial ports, four
precision clock generators, an input data port, an S/PDIF
transceiver, an 8-channel asynchronous sample rate con-
verter, and a signal routing unit
Rev. C
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Page 2 of 56
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January 2008
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