1200 MHz to 3600 MHz Rx Mixer with
Integrated Fractional-N PLL and VCO
ADRF6604
Data Sheet
The PLL can support input reference frequencies from 12 MHz
to 160 MHz. The PFD output controls a charge pump whose
output drives an off-chip loop filter.
FEATURES
Rx mixer with integrated fractional-N PLL
RF input frequency range: 1200 MHz to 3600 MHz
Internal LO frequency range: 2500 MHz to 2900 MHz
Input P1dB: 14.5 dBm
Input IP3: 27.5 dBm
IIP3 optimization via external pin
SSB noise figure
The loop filter output is then applied to an integrated VCO. The
VCO output at 2 × fLO is applied to an LO divider, as well as to a
programmable PLL divider. The programmable PLL divider is
controlled by a sigma-delta (Σ-Δ) modulator (SDM). The modulus
of the SDM can be programmed from 1 to 2047.
IP3SET pin open: 14.3 dB
IP3SET pin at 3.3 V: 15.5 dB
The active mixer converts the single-ended, 50 Ω RF input to
a differential, 200 Ω IF output. The IF output can operate up
to 500 MHz.
Voltage conversion gain: 6.8 dB
Matched 200 Ω IF output impedance
IF 3 dB bandwidth: 500 MHz
Programmable via 3-wire SPI interface
40-lead, 6 mm × 6 mm LFCSP
The ADRF6604 is fabricated using an advanced silicon-germanium
BiCMOS process. It is available in a 40-lead, RoHS-compliant,
6 mm × 6 mm LFCSP with an exposed paddle. Performance is
specified over the −40°C to +85°C temperature range.
APPLICATIONS
Table 1.
Cellular base stations
Internal LO
Range
3 dB RFIN
Balun Range
1 dB RFIN
Balun Range
Part No.
GENERAL DESCRIPTION
ADRF6601 750 MHz
1160 MHz
300 MHz
450 MHz
The ADRF6604 is a high dynamic range active mixer with
integrated phase-locked loop (PLL) and voltage controlled
oscillator (VCO). The PLL/synthesizer uses a fractional-N
PLL to generate a fLO input to the mixer. The reference input
can be divided or multiplied and then applied to the PLL phase
frequency detector (PFD).
2500 MHz
1000 MHz
3100 MHz
1100 MHz
3200 MHz
1200 MHz
3600 MHz
1600 MHz
1350 MHz
2750 MHz
1450 MHz
2850 MHz
1600 MHz
3200 MHz
ADRF6602 1550 MHz
2150 MHz
ADRF6603 2100 MHz
2600 MHz
ADRF6604 2500 MHz
2900 MHz
FUNCTIONAL BLOCK DIAGRAM
VCC1
1
VCC2 VCC_LO VCC_MIX VCC_V2I VCC_LO
NC NC
10
17
22
27
34
32
33
36
LODRV_EN
LON 37
38
ADRF6604
3.3V
LDO
2
9
DECL3P3
INTERNAL LO RANGE
2500MHz TO 2900MHz
BUFFER
BUFFER
2.5V
LDO
DECL2P5
DECLVCO
LOP
VCO
LDO
PLL_EN 16
DIV
2:1
40
BY
2, 1
INTEGER
REG
FRACTION
REG
MUX
12
DATA
MODULUS
SPI
13
14
CLK
LE
INTERFACE
26
29
RF
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
IN
VCO
CORE
IP3SET
×2
N COUNTER
21 TO 123
PRESCALER
÷2
6
8
REF_IN
MUX
÷2
CHARGE PUMP
250µA,
500µA (DEFAULT),
–
+
PHASE
FREQUENCY
DETECTOR
TEMP
SENSOR
÷4
750µA,
1000µA
5
MUXOUT
4
7
11 15 20 21 23 24 25 28 30 31 35
GND
39
18 19
3
R
CP VTUNE IFP IFN
SET
Figure 1.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com