Broadband Up/Downconverting Mixer with
Integrated Fractional-N PLL and VCO
ADRF6655
The programmable divider is controlled by an Σ-Δ modulator
(SDM). The modulus of the SDM can be programmed between
FEATURES
Broadband active mixer with integrated fractional-N PLL
RF input frequency range: 100 MHz to 2500 MHz
Internal LO frequency range: 1050 MHz to 2300 MHz
Flexible IF output interface
1 and 2047.
The broadband, active mixer employs a bias adjustment to allow
for enhanced IP3 performance at the expense of increased supply
current. The mixer provides an input IP3 exceeding 25 dBm
with 12 dB single sideband NF under typical conditions. The IIP3
can be boosted to ~29 dBm with roughly 20 mA of additional
supplied current. The mixer provides a typical voltage conversion
gain of 6 dB with a 200 Ω differential IF output impedance. The
IF output can be externally matched to support upconversion over
a limited frequency range.
Input P1dB: 12 dBm
Input IP3: 29 dBm
Noise figure (SSB): 12 dB
Voltage conversion gain: 6 dB
Matched 200 Ω output impedance
SPI serial interface for PLL programming
40-lead 6 mm × 6 mm LFCSP
The ADRF6655 is fabricated using an advanced silicon-germanium
BiCMOS process. It is packaged in a 40-lead, exposed-paddle,
Pb-free, 6 mm × 6 mm LFCSP. Performance is specified over a
−40°C to +85°C temperature range.
GENERAL DESCRIPTION
The ADRF6655 is a high dynamic range active mixer with
integrated PLL and VCO. The synthesizer uses a programmable
integer-N/fractional-N PLL to generate a local oscillator input
to the mixer. The PLL reference input is nominally 20 MHz. The
reference input can be divided by or multiplied by and then
applied to the PLL phase detector. The PLL can support input
reference frequencies from 10 MHz to 160 MHz. The phase
detector output controls a charge pump whose output is integrated
in an off-chip loop filter. The loop filter output is then applied to an
integrated VCO. The VCO output at 2 × fLO is then applied to a local
oscillator (LO) divider as well as to a programmable PLL divider.
FUNCTIONAL BLOCK DIAGRAM
GND GND VCCLO
NC
33
NC GND
32 31
36
35
34
30
29
28
27
GND
LOSEL
LON 37
IP3SET
GND
ADRF6655
BUFFER
BUFFER
38
LOP
VCCMIX
INTEGER
REG
26
25
FRACTION
INP
INN
DIVIDER
÷2 OR ÷3
MODULUS
MUX
11
GND
DATA
CLK
LE
REG
12
13
14
15
LOSEL
SPI
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
INTERFACE
VCO
CORE
N COUNTER
21 TO 123
GND
24
23
22
21
PRESCALER
GND
×2
GND
6
7
REFIN
GND
–
+
PHASE
FREQUENCY
DETECTOR
MUX
÷2
CHARGE PUMP
250µA,
500µA (DEFAULT),
750µA,
VCCV2I
GND
TEMP
SENSOR
÷4
3.3V LDO
2.5V LDO
10
VCO LDO
40 16
1000µA
8
MUXOUT
1
2
3
4
5
9
39
17
18
19
20
VCC1
DECL1
CP GND RSET DECL2 VCC2 VTUNE DECL3 NC VCCLO OUTN OUTP GND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2010 Analog Devices, Inc. All rights reserved.
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