Wideband Quadrature Modulator with
Integrated Fractional-N PLL and VCOs
Data Sheet
ADRF6720-27
FEATURES
GENERAL DESCRIPTION
I/Q modulator with integrated fractional-N PLL
RF output frequency range: 400 MHz to 3000 MHz
Internal LO frequency range: 356.25 MHz to 2855 MHz
Output P1dB: 10.8 dBm at 2140 MHz
The ADRF6720-27 is a wideband quadrature modulator with an
integrated synthesizer ideally suited for 3G and 4G com-
munication systems. The ADRF6720-27 consists of a high
linearity broadband modulator, an integrated fractional-N
phase-locked loop (PLL), and four low phase noise multicore
voltage controlled oscillators (VCOs).
Output IP3: 31.1 dBm at 2140 MHz
Carrier feedthrough: −44.3 dBm at 2140 MHz
Sideband suppression: −40.8 dBc at 2140 MHz
Noise floor: −159.5 dBm/Hz at 2140 MHz
Baseband 1 dB modulation bandwidth: >1000 MHz
Baseband input bias level: 2.68 V
Power supply: 3.3 V/425 mA
Integrated RF tunable balun allowing single-ended RF output
Multicore integrated VCOs
The ADRF6720-27 local oscillator (LO) signal can be generated
internally via the on-chip integer-N and fractional-N synthesizers,
or externally via a high frequency, low phase noise LO signal.
The internal integrated synthesizer enables LO coverage from
356.25 MHz to 2855 MHz using the multicore VCOs. In the
case of internal LO generation or external LO input, quadrature
signals are generated with a divide by 2 phase splitter. When the
ADRF6720-27 is operated with an external 1 × LO input, a
polyphase filter generates the quadrature inputs to the mixer.
HD3/IP3 optimization
Sideband suppression and carrier feedthrough optimization
High-side/low-side LO injection
The ADRF6720-27 offers digital programmability for carrier
feedthrough optimization, sideband suppression, HD3/IP3
optimization, and high-side or low-side LO injection.
Programmable via 3-wire serial port interface (SPI)
40-lead 6 mm × 6 mm LFCSP
APPLICATIONS
The ADRF6720-27 is fabricated using an advanced silicon-
germanium BiCMOS process. It is available in a 40-lead,
RoHS-compliant, 6 mm × 6 mm LFCSP package with an
exposed pad. Performance is specified over the −40°C to +85°C
temperature range.
2G/3G/4G/LTE broadband communication systems
Microwave point-to-point radios
Satellite modems
Military/aerospace
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
VPOSx
40
35
30
26
22
17
11
6
I+
I–
3
4
27
24
ENBL
ADRF6720-27
V TO I
PHASE
CORRECTION
LO NULLING
DAC
RFOUT
LO NULLING
DAC
PHASE
CORRECTION
8
Q–
Q+
V TO I
PLL
18
19
LOOUT+
LOOUT–
9
39
36
REFIN
CP
QUAD
DIVIDER
32
VTUNE
LOIN–
LOIN+
33
34
15
14
13
CS
SERIAL
POLYPHASE
FILTER
LDO
2.5V
LDO
VCO
SCLK
SDIO
PORT
INTERFACE
2
5
7 10 16 20 23 25 29 37 38
12
31
28
DECL1 DECL2
DECL3
GND
Figure 1.
Rev. B
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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