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ADP3190JRQZ-RL PDF预览

ADP3190JRQZ-RL

更新时间: 2024-11-01 20:15:23
品牌 Logo 应用领域
安森美 - ONSEMI 开关光电二极管
页数 文件大小 规格书
27页 430K
描述
SWITCHING CONTROLLER, 4000kHz SWITCHING FREQ-MAX, PDSO28, LEAD FREE, MO-137AF, QSOP-28

ADP3190JRQZ-RL 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP, SSOP28,.25
针数:28Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.65Is Samacsys:N
其他特性:CAN BE CONFIGURED AS CURRENT MODE模拟集成电路 - 其他类型:SWITCHING CONTROLLER
控制模式:VOLTAGE-MODE控制技术:PULSE WIDTH MODULATION
最大输入电压:5.25 V最小输入电压:4.75 V
标称输入电压:5 VJESD-30 代码:R-PDSO-G28
JESD-609代码:e3长度:9.906 mm
湿度敏感等级:1功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP28,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.7526 mm子类别:Switching Regulator or Controllers
表面贴装:YES切换器配置:PHASE-SHIFT
最大切换频率:4000 kHz温度等级:COMMERCIAL EXTENDED
端子面层:TIN端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9116 mm
Base Number Matches:1

ADP3190JRQZ-RL 数据手册

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6-Bit, Programmable 2-/3-/4-Phase,  
Synchronous Buck Controller  
ADP3190  
FEATURES  
Selectable 2-, 3-, or 4-phase operation at up to  
1 MHz per phase  
9.5 mV worst-case differential sensing error  
over temperature  
Logic-level PWM outputs for interface to external  
high power drivers  
PWM Flex-ModeTM architecture for excellent load  
transient performance  
Active current balancing between all output phases  
Built-in power-good/crowbar blanking supports on-the-fly  
VID code changes  
FUNCTIONAL BLOCK DIAGRAM  
VCC  
28  
RAMPADJ  
14  
RT  
13  
SHUNT  
REGULATOR  
(ADP3190 ONLY)  
OSCILLATOR  
UVLO  
11  
19  
EN  
SHUTDOWN  
AND BIAS  
SET  
EN  
27  
26  
25  
24  
RESET  
PWM1  
PWM2  
PWM3  
PWM4  
CMP  
GND  
DAC  
+150mV  
RESET  
CMP  
CSREF  
CURRENT  
BALANCING  
CIRCUIT  
2-/3-/4-PHASE  
DRIVER LOGIC  
RESET  
RESET  
CMP  
DAC  
–250mV  
CMP  
6-bit, digitally programmable 0.8375 V to 1.6 V output  
Programmable short circuit protection with programmable  
latch-off delay  
10  
PWRGD  
DELAY  
CROWBAR  
CURRENT  
LIMIT  
23  
22  
21  
20  
SW1  
SW2  
SW3  
SW4  
APPLICATIONS  
Desktop PC power supplies for  
Next generation Intel® processors  
VRM modules  
15  
ILIMIT  
EN  
Game consoles  
17  
16  
18  
CSSUM  
CSREF  
CURRENT  
LIMIT  
CIRCUIT  
GENERAL DESCRIPTION  
12  
DELAY  
The ADP31901 is a highly efficient, multiphase, synchronous  
buck switching regulator controller optimized for converting a  
5 V (ADP3190A) or 12 V (ADP3190) main supply into the core  
supply voltage required by high performance Intel processors.  
The part uses an internal 6-bit DAC to read a voltage identifica-  
tion (VID) code directly from the processor, which is used to  
set the output voltage between 0.8375 V and 1.6 V. The devices  
use a multimode PWM architecture to drive the logic-level  
outputs at a programmable switching frequency that can be  
optimized for VR size and efficiency. The phase relationship of  
the output signals can be programmed to provide 2-, 3-, or 4-  
phase operation, allowing for the construction of up to four  
complementary buck switching stages.  
CSCOMP  
SOFT  
START  
8
FB  
9
COMP  
PRECISION  
REFERENCE  
VID  
DAC  
ADP3190  
7
1
2
3
4
5
6
FBRTN  
VID4 VID3 VID2 VID1 VID0 VID5  
Figure 1.  
The ADP3190 is a replacement for the ADP3188. A built-in  
shunt regulator allows the part to be connected to the 12 V  
system supply through a series resistor.  
The ADP3190 includes programmable, no-load offset and slope  
functions to adjust the output voltage as a function of the load  
current, so it is always optimally positioned for a system  
transient. The ADP3190 also provides accurate and reliable  
short-circuit protection, adjustable current limiting, and a  
delayed power-good output that accommodates on-the-fly  
output voltage changes requested by the CPU.  
The device is specified over the commercial temperature  
range of 0°C to 85°C and is available in a 28-lead TSSOP and  
a 28-lead QSOP.  
1
Protected by U. S. Patent Number 6,683,441; other patents pending.  
©2008 SCILLC. All rights reserved.  
January 2008 – Rev. 2  
Publication Order Number:  
ADP3190/D  

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