Datasheet > ADN4652

ADN4652

更新时间： 2024-11-06 11:16:15

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
24页	795K
描述
5 kV/3.75 kV rms、600 Mbps双通道LVDS隔离器

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ADN4652 数据手册

5 kV RMS, 600 Mbps,

Dual-Channel LVDS Isolators

Data Sheet

ADN4650/ADN4651/ADN4652

FEATURES

FUNCTIONAL BLOCK DIAGRAMS

IN1

IN2

5 kV rms LVDS isolator

ADN4650

Complies with TIA/EIA-644-A LVDS standard

Multiple dual-channel configurations

Up to 600 Mbps switching with low jitter

4.5 ns maximum propagation delay

151 ps maximum peak-to-peak total jitter at 600 Mbps

100 ps maximum pulse skew

600 ps maximum part to part skew

ISOLATION

BARRIER

LDO

DD2

DD1

IN1+

IN1–

OUT1+

OUT1–

LVDS

DIGITAL ISOLATOR

LVDS

IN2+

OUT2+

IN2–

OUT2–

2.5 V or 3.3 V supplies

−75 dBc power supply ripple rejection and glitch immunity

8 kV IEC 61000-4-2 ESD protection across isolation barrier

High common-mode transient immunity: >25 kV/μs

Passes EN55022 Class B radiated emissions limits with

600 Mbps PRBS or 300 MHz clock

GND

Figure 1.

IN1

IN2

ADN4651

ISOLATION

BARRIER

LDO

DD2

Safety and regulatory approvals

DD1

UL (pending): 5000 V rms for 1 minute per UL 1577

CSA Component Acceptance Notice 5A (pending)

VDE certificate of conformity (pending)

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12

IN1+

OUT1+

IN1–

OUT1–

LVDS

DIGITAL ISOLATOR

LVDS

OUT2+

IN2+

_IORM= 424 V peak

OUT2–

IN2–

Fail-safe output high for open, short, and terminated input

conditions (ADN4651/ADN4652)

GND

Figure 2.

Operating temperature range: −40°C to +125°C

20-lead SOIC with 7.8 mm creepage/clearance

IN1

IN2

ADN4652

ISOLATION

BARRIER

APPLICATIONS

LDO

DD2

DD1

Analog front-end (AFE) isolation

Data plane isolation

Isolated high speed clock and data links

Isolated serial peripheral interface (SPI) over LVDS

IN1+

IN1–

OUT1+

OUT1–

LVDS

DIGITAL ISOLATOR

LVDS

OUT2+

OUT2–

IN2+

GENERAL DESCRIPTION

IN2–

The ADN4650/ADN4651/ADN4652¹are signal isolated, low

voltage differential signaling (LVDS) buffers that operate at up

to 600 Mbps with very low jitter.

GND

Figure 3.

The devices integrate Analog Devices, Inc., iCoupler® technology,

enhanced for high speed operation, to provide galvanic isolation of

the TIA/EIA-644-A compliant LVDS drivers and receivers. This

technology allows drop-in isolation of an LVDS signal chain.

For high speed operation with low jitter, the LVDS and isolator

circuits rely on a 2.5 V supply. An integrated on-chip low dropout

regulator (LDO) can provide the required 2.5 V from an external

3.3 V power supply. The devices are fully specified over a wide

industrial temperature range and are available in a 20-lead,

wide-body SOIC package with 5 kV rms isolation.

Multiple channel configurations are offered, and the LVDS receiv-

ers on the ADN4651/ADN4652 include a fail-safe mechanism

to ensure a Logic 1 on the corresponding LVDS driver output

when the inputs are floating, shorted, or terminated, but not driven.

¹Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.

Rev. B Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

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