Datasheet > ADN2891ACP-RL7

ADN2891ACP-RL7

更新时间： 2024-01-05 20:19:50

品牌	Logo	应用领域
亚德诺 - ADI		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
16页	564K
描述
IC SPECIALTY TELECOM CIRCUIT, QCC16, 3 X 3 MM, MO-220-VEED-2, LFCSP-16, Telecom IC:Other

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ADN2891ACP-RL7 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFN
包装说明：	HVQCCN, LCC16,.12SQ,20	针数：	16
Reach Compliance Code：	not_compliant	HTS代码：	8542.39.00.01
风险等级：	5.7	JESD-30 代码：	S-XQCC-N16
JESD-609代码：	e0	长度：	3 mm
湿度敏感等级：	3	功能数量：	1
端子数量：	16	最高工作温度：	95 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装等效代码：	LCC16,.12SQ,20
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	3.3 V
认证状态：	Not Qualified	座面最大高度：	1 mm
子类别：	ATM/SONET/SDH ICs	最大压摆率：	0.06 mA
标称供电电压：	3.3 V	表面贴装：	YES
电信集成电路类型：	TELECOM CIRCUIT	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15) - with Silver (Ag) barrier	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	3 mm
Base Number Matches：	1

ADN2891ACP-RL7 数据手册

ADN2891

APPLICATIONS

The exposed pad should connect to the GND plane using filled

vias so that solder does not leak through the vias during reflow.

Using filled vias in parallel under the package greatly reduces

the thermal resistance and enhances the reliability of the

connectivity of the exposed pad to the GND plane during

reflow.

PCB DESIGN GUIDELINES

Proper RF PCB design techniques must be used to ensure

optimal performance.

Output Buffer Power Supply and Ground Planes

Pin 9 (DRVEE) and Pin 12 (DRVCC) are the power supply and

ground pins that provide current to the differential output

buffer. To reduce possible series inductance, Pin 9, which is the

ground return of the output buffer, should connect to ground

directly. If the ground plane is an internal plane and

To reduce power noise, a 10 μF electrolytic decoupling capacitor

between power and ground should be close to where the 3.3 V

supply enters the PCB. The other 0.1 μF and 1 nF ceramic chip

decoupling capacitors should be close to the VCC and VEE pins

to provide better decouple filtering and a shorter current return

loop.

connections to the ground plane are vias, multiple vias in

parallel to ground can reduce series inductance.

Similarly, to reduce the possible series inductance, Pin 12,

which supplies power to the high speed differential

OUTP/OUTN output buffer, should connect to the power plane

directly. If the power plane is an internal plane and connections

to the power plane are vias, multiple vias in parallel can reduce

the series inductance, especially on Pin 12. See Figure 20 for the

recommended connections.

VCC

RSSI MEASUREMENT

TO ADC

C10

0.1μF

VCC

AVCC

DRVCC

ADN2891

OUTP C3

OUTN C4

DRVEE

CONNECT

EXPOSED

PAD TO

GND

TO HOST

BOARD

NIN

ADN2880

AVEE

C1–C4, C11: 0.01μF X5R/X7R DIELECTRIC, 0201 CASE

C5, C7, C9, C10, C12: 0.1μF X5R/X7R DIELECTRIC, 0402 CASE

C6, C8: 1nF X5R/X7R DIELECTRIC, 0201 CASE

C11

4.7kΩ TO 10kΩ

ON HOST BOARD

C12

VCC

Figure 20. Typical Applications Circuit (Example of Using PIN PD and On-Chip RSSI Detector)

Rev. A | Page 11 of 16

1...8 9 101112 13 14...16

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