Continuous Rate 6.5 Mbps to 8.5 Gbps Clock and
Data Recovery IC with Integrated Limiting Amp/EQ
Data Sheet
ADN2913
FEATURES
GENERAL DESCRIPTION
Serial data input: 6.5 Mbps to 8.5 Gbps
No reference clock required
The ADN2913 provides the receiver functions of quantization,
signal level detection, and clock and data recovery for continuous
data rates from 6.5 Mbps to 8.5 Gbps. The ADN2913 automatically
locks to all data rates without the need for an external reference
clock or programming. ADN2913 jitter performance exceeds all
jitter specifications required by SONET/SDH, including jitter
transfer, jitter generation, and jitter tolerance.
Exceeds SONET/SDH requirements for jitter transfer/
generation/tolerance
Quantizer sensitivity: 6.3 mV typical (limiting amplifier mode)
Optional limiting amplifier, equalizer (EQ), and 0 dB EQ inputs
Programmable jitter transfer bandwidth to support G.8251 OTN
Programmable slice level
The ADN2913 provides manual or automatic slice adjust and
manual sample phase adjusts. Additionally, the user can select a
limiting amplifier, equalizer, or 0 dB EQ at the input. The equalizer
is adaptive or it can be manually set.
Sample phase adjust (5.65 Gbps or greater)
Output polarity invert
Programmable LOS threshold via I2C
I2C interface to access optional features
Loss of signal (LOS) alarm (limiting amplifier mode only)
Loss of lock (LOL) indicator
PRBS generator/detector
Application aware power
352 mW at 8.5 Gbps, equalizer mode, no clock output
380 mW at 6.144 Gbps, limiting amplifier mode,
no clock output
340 mW at 622 Mbps, 0 dB EQ mode, no clock output
Power supplies: 1.2 V, flexible 1.8 V to 3.3 V, and 3.3 V
4 mm × 4 mm, 24-lead LFCSP
The receiver front-end loss of signal (LOS) detector
circuit indicates when the input signal level falls below a user-
programmable threshold. The LOS detection circuit has hysteresis
to prevent chatter at the LOS output. In addition, the input signal
strength can be read through the I2C registers.
The ADN2913 also supports pseudorandom binary sequence
(PRBS) generation, bit error detection, and input data rate
readback features.
The ADN2913 is available in a compact 4 mm × 4 mm, 24-lead
lead frame chip scale package (LFCSP). All ADN2913 specifica-
tions are defined over the ambient temperature range of −40°C
to +85°C, unless otherwise noted.
APPLICATIONS
SONET/SDH OC-1/OC-3/OC-12/OC-48 and all associated
FEC rates
1GE, 1GFC, 2GFC, 4GFC, 8GFC, CPRI OS/L.6 up to OS/L.60
Any rate regenerators/repeaters
FUNCTIONAL BLOCK DIAGRAM
REFCLKP/
REFCLKN
(OPTIONAL)
DATOUTP/
DATOUTN
CLKOUTP/
CLKOUTN
SCK
SDA
LOL
DATA RATE
2
2
I C REGISTERS
FREQUENCY
ACQUISITION
AND LOCK
I C_ADDR
CML
CML
DETECTOR
CLK
DDR
ADN2913
LOS
DETECT
LOS
FIFO
SAMPLE
PHASE
÷N
÷2
ADJUST
DOWNSAMPLER
AND LOOP
FILTER
DCO
LA
DATA
INPUT
SAMPLER
PIN
NIN
2
RXD
0dB EQ
EQ
RXCK
50Ω
50Ω
CLOCK
2
PHASE
I C
2
I C
SHIFTER
V
V
CC
CM
FLOAT
Figure 1.
Rev. A
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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