Datasheet > ADN2891ACP-RL7

ADN2891ACP-RL7

更新时间： 2024-01-06 07:16:29

品牌	Logo	应用领域
亚德诺 - ADI		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
16页	564K
描述
IC SPECIALTY TELECOM CIRCUIT, QCC16, 3 X 3 MM, MO-220-VEED-2, LFCSP-16, Telecom IC:Other

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

ADN2891ACP-RL7 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFN
包装说明：	HVQCCN, LCC16,.12SQ,20	针数：	16
Reach Compliance Code：	not_compliant	HTS代码：	8542.39.00.01
风险等级：	5.7	JESD-30 代码：	S-XQCC-N16
JESD-609代码：	e0	长度：	3 mm
湿度敏感等级：	3	功能数量：	1
端子数量：	16	最高工作温度：	95 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装等效代码：	LCC16,.12SQ,20
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	3.3 V
认证状态：	Not Qualified	座面最大高度：	1 mm
子类别：	ATM/SONET/SDH ICs	最大压摆率：	0.06 mA
标称供电电压：	3.3 V	表面贴装：	YES
电信集成电路类型：	TELECOM CIRCUIT	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15) - with Silver (Ag) barrier	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	3 mm
Base Number Matches：	1

ADN2891ACP-RL7 数据手册

ADN2891

THEORY OF OPERATION

LIMITING AMPLIFIER

LOSS OF SIGNAL (LOS) DETECTOR

Input Buffer

The on-chip LOS circuit drives LOS to logic high when the

input signal level falls below a user-programmable threshold.

The threshold level can be set to anywhere from 3.5 mV p-p to

35 mV p-p, typical, and is set by a resistor connected between

the THRADJ pin and VEE. See Figure 8 and Figure 9 for the

LOS threshold vs. THRADJ. The ADN2891 LOS circuit has an

electrical hysteresis greater than 2.5 dB to prevent chatter at the

LOS signal. The LOS output is an open-collector output that

must be pulled up externally with a 4.7 kΩ to 10 kΩ resistor.

The ADN2891 limiting amplifier provides differential inputs

(PIN/NIN), each having single-ended, on-chip, 50 Ω termina-

tion. The amplifier can accept either dc-coupled or ac-coupled

signals; however, an ac-coupled signal is recommended. Using a

dc-coupled signal, the amplifier needs a correct input common-

mode voltage and enough headroom to handle the dynamic

input signal strength. Additionally, TIA output offset drifts may

degrade receiver performance.

RECEIVED SIGNAL STRENGTH INDICATOR (RSSI)

The ADN2891 limiting amplifier is a high gain device. It is

susceptible to dc offsets in the signal path. The pulse width

distortion presented in the NRZ data or a distortion generated

by the TIA may appear as dc offset or a corrupted signal to the

ADN2891 inputs. An internal offset correction loop can

compensate for certain levels of offset. To compensate for more

offset, an external capacitor connected between the CAZ1 and

CAZ2 pins maybe necessary. For GbE and FC applications, no

external capacitor is necessary; however, for SONET appli-

cations, a 0.01 μF capacitor helps the input signal offset

compensation and provides a 3 dB cutoff frequency at 1 kHz.

The ADN2891 has an on-chip, RSSI circuit. By monitoring the

current supplied to the photodiode, the RSSI circuit provides an

accurate, average power measurement. The output of the RSSI is

a current that is directly proportional to the average amount of

PIN photodiode current. Placing a resistor between the

RSSI_OUT pin and GND converts the current to a GND

referenced voltage. This function eliminates the need for

external RSSI circuitry for SFF-8472-compliant optical

receivers. For more information, see Figure 14 to Figure 18.

SQUELCH MODE

CML Output Buffer

Driving the SQUELCH input to logic high disables the limiting

amplifier outputs. Using LOS output to drive the SQUELCH

input, the limiting amplifier outputs stop toggling anytime a

signal input level to the limiting amplifier drops below the

programmed LOS threshold.

The ADN2891 provides differential CML outputs, OUTP and

OUTN. Each output has an internal 50 Ω termination to VCC.

The SQUELCH pin has a 100 kΩ, internal, pull-down resistor.

Rev. A | Page 10 of 16

1...7 8 91011 12 13...16

下载PDF

与ADN2891ACP-RL7相关器件

型号	品牌	描述	获取价格	数据表
ADN2891ACPZ-500RL7	ADI	3.3 V, 3.2 Gbps, Limiting Amplifier	获取价格
ADN2891ACPZ-RL	ADI	3.3 V, 3.2 Gbps, Limiting Amplifier	获取价格
ADN2891ACPZ-RL7	ADI	3.3 V, 3.2 Gbps, Limiting Amplifier	获取价格
ADN2892	ADI	3.3 V 4.25 Gb/s Limiting Amplifier	获取价格
ADN2892ACP-RL	ADI	3.3 V 4.25 Gb/s Limiting Amplifier	获取价格
ADN2892ACP-RL7	ADI	3.3 V 4.25 Gb/s Limiting Amplifier	获取价格

与ADN2891ACP-RL7相关文章

SG3525资料手册详解：SG3525参数分析、引脚说明、应用介绍
2024-05-23

3
AT89C51单片机资料手册详细解析及应用示例
2024-05-23

5
CP2102资料手册解读：CP2102引脚说明、关键参数分析
2024-05-23

3
资料手册解读：UC3842参数和管脚说明
2024-05-22

5

产品中心

服务支持

精选活动

关于我们

帮助中心

ADN2891ACP-RL7

ADN2891ACP-RL7 技术参数

ADN2891ACP-RL7 数据手册

与ADN2891ACP-RL7相关器件

与ADN2891ACP-RL7相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

ADN2891ACP-RL7

ADN2891ACP-RL7 技术参数

ADN2891ACP-RL7 数据手册

与ADN2891ACP-RL7相关器件

与ADN2891ACP-RL7相关文章

您还可以找

您在本页遇到什么问题？