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ADN2530YCPZ-500R7 PDF预览

ADN2530YCPZ-500R7

更新时间： 2024-01-31 06:08:50
品牌 Logo 应用领域
亚德诺 - ADI 接口集成电路
页数 文件大小 规格书
20页 377K
描述
11.3 Gbps, Active Back-Termination, Differential VCSEL Driver

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ADN2530YCPZ-500R7 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN,针数：16
Reach Compliance Code：unknown风险等级：5.64
接口集成电路类型：INTERFACE CIRCUITJESD-30 代码：S-PQCC-N16
JESD-609代码：e3长度：3 mm
湿度敏感等级：3功能数量：1
端子数量：16最高工作温度：100 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
认证状态：COMMERCIAL座面最大高度：0.9 mm
最大供电电压：3.53 V最小供电电压：3.07 V
标称供电电压：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3 mmBase Number Matches：1

ADN2530YCPZ-500R7 数据手册

 浏览型号ADN2530YCPZ-500R7的Datasheet PDF文件第13页浏览型号ADN2530YCPZ-500R7的Datasheet PDF文件第14页浏览型号ADN2530YCPZ-500R7的Datasheet PDF文件第15页浏览型号ADN2530YCPZ-500R7的Datasheet PDF文件第17页浏览型号ADN2530YCPZ-500R7的Datasheet PDF文件第18页浏览型号ADN2530YCPZ-500R7的Datasheet PDF文件第19页 
ADN2530  
Data Sheet  
Assuming the dc voltage drop across L1, L2, L3, and L4 = 0 V  
and IMOD = 10 mA, the minimum voltage at the modulation  
output pins is equal to  
DESIGN EXAMPLE  
This design example covers:  
•
•
Headroom calculations for IBIAS, IMODP, and IMODN pins.  
VCC − (IMOD × 50)/2 = VCC − 0.25  
Calculation of the typical voltage required at the BSET  
and MSET pins to produce the desired bias and  
modulation currents.  
VCC − 0.25 > VCC − 0.7 V, which satisfies the requirement  
The maximum voltage at the modulation output pins is equal to  
VCC + (IMOD × 50)/2 = VCC + 0.25  
•
Calculations of the IBIAS monitor accuracy over the IBIAS  
current range.  
VCC + 0.25 < VCC + 0.7 V, which satisfies the requirement  
This design example assumes that the impedance of the  
TOSA is 60 Ω, the forward voltage of the VCSEL at low current  
is VF = 1.2 V, IBIAS = 10 mA, IMOD = 10 mA, and VCC = 3.3 V.  
Headroom calculations must be repeated for the minimum and  
maximum values of the required IBIAS and IMOD ranges to  
ensure proper device operation over all operating conditions.  
Headroom Calculations  
BSET and MSET Pin Voltage Calculation  
To ensure proper device operation, the voltages on the IBIAS,  
IMODP, and IMODN pins must meet the compliance voltage  
specifications in Table 1.  
To set the desired bias and modulation currents, the BSET and  
MSET pins of the ADN2530 must be driven with the appropriate  
dc voltage. The voltage range required at the BSET pin to generate  
the required IBIAS range can be calculated using the BSET voltage  
to IBIAS gain specified in Table 1. Assuming that IBIAS = 10 mA  
and the typical IBIAS/VBSET ratio of 20 mA/V, the BSET voltage  
is given by  
Considering the typical application circuit shown in Figure 39,  
the voltage at the IBIAS pin can be written as  
V
IBIAS = VCC − VF − (IBIAS × RTOSA) − VLA  
where:  
IBIAS (mA)  
20 mA/V  
10  
20  
VBSET  
=
=
= 0.5 V  
VCC is the supply voltage.  
VF is the forward voltage across the laser at low current.  
The BSET voltage range can be calculated using the required  
IBIAS range and the minimum and maximum BSET voltage to  
IBIAS gain values specified in Table 1.  
R
TOSA is the resistance of the TOSA.  
LA is the dc voltage drop across L5, L6, L7, and L8.  
V
For proper operation, the minimum voltage at the IBIAS pin  
should be greater than 0.55 V, as specified by the minimum  
IBIAS compliance specification in Table 1.  
The voltage required at the MSET pin to produce the desired  
modulation current can be calculated using  
IMOD  
K
VMSET  
=
Assuming that the voltage drop across the 50 Ω transmission lines  
is negligible and that VLA = 0 V, V F = 1.2 V, and IBIAS = 10 mA,  
where K is the MSET voltage to IMOD ratio.  
V
V
IBIAS = 3.3 − 1.2 − (0.01 × 60) = 1.5 V  
The value of K depends on the actual resistance of the TOSA  
and can be obtained from Figure 34. For a TOSA resistance of  
60 Ω, the typical value of K = 24 mA/V. Assuming that IMOD =  
10 mA and using the preceding equation, the MSET voltage is  
given by  
IBIAS = 1.5 V > 0.55 V, which satisfies the requirement  
The maximum voltage at the IBIAS pin must be less than the  
maximum IBIAS compliance specification as described by  
V
COMPLIANCE_MAX = VCC − 0.75 − 22 × IBIAS (A)  
For this example,  
VCOMPLIANCE_MAX = VCC – 0.75 − 22 × 0.01 = 2.33 V  
IBIAS = 1.5 V < 2.33 V, which satisfies the requirement  
IMOD (mA)  
24 mA/V  
10  
24  
VMSET  
=
=
= 0.42 V  
The MSET voltage range can be calculated using the required  
IMOD range and the minimum and maximum K values. These can  
be obtained from the minimum and maximum curves in Figure 34.  
V
To calculate the headroom at the modulation current pins  
(IMODP and IMODN), the voltage has a dc component equal  
to VCC due to the ac-coupled configuration and a swing equal  
to IMOD × 50 Ω, as RTOSA < 100 Ω. For proper operation of the  
ADN2530, the voltage at each modulation output pin should be  
within the normal operation region shown in Figure 35.  
Rev. B | Page 16 of 20  
 
 
 
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