Datasheet > ADN2807ACP

ADN2807ACP

更新时间： 2024-01-14 22:08:43

品牌	Logo	应用领域
亚德诺 - ADI		放大器时钟
页数	文件大小	规格书
20页	354K
描述
155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp

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ADN2807ACP 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	LFCSP-48	针数：	48
Reach Compliance Code：	compliant	ECCN代码：	5A991.B.3
HTS代码：	8542.39.00.01	风险等级：	5.28
应用程序：	SONET;SDH	JESD-30 代码：	S-XQCC-N48
JESD-609代码：	e3	长度：	7 mm
湿度敏感等级：	3	功能数量：	1
端子数量：	48	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装等效代码：	LCC48,.27SQ,20
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	电源：	3.3 V
认证状态：	Not Qualified	座面最大高度：	1 mm
子类别：	ATM/SONET/SDH ICs	最大压摆率：	0.215 mA
标称供电电压：	3.3 V	表面贴装：	YES
技术：	BIPOLAR	电信集成电路类型：	ATM/SONET/SDH CLOCK RECOVERY CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	7 mm

ADN2807ACP 数据手册

155/622 Mb/s Clock and Data Recovery IC

with Integrated Limiting Amp

ADN2807

GENERAL DESCRIPTION

FEATURES

Meets SONET requirements for jitter transfer/

generation/tolerance

Quantizer sensitivity: 4 mV typical

Adjustable slice level: 100 mV

Patented clock recovery architecture

Loss-of-signal detect range: 3 mV to 15 mV

Single-reference clock frequency for all rates, including

15/14 (7%) wrapper rate

Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or

155.52 MHz REFCLK

REFCLK inputs: LVPECL/LVDS/LVCMOS/LVTTL compatible

(LVPECL/LVDS only at 155.52 MHz)

Optional 19.44 MHz on-chip oscillator to be used with

external crystal

Loss-of-lock indicator

The ADN2807 provides the receiver functions of quantization,

signal level detect, and clock and data recovery at rates of OC-3,

OC-12, and 15/14 FEC. All SONET jitter requirements are met,

including jitter transfer, jitter generation, and jitter tolerance. All

specifications are quoted for –40°C to +85°C ambient

temperature, unless otherwise noted.

The device is intended for WDM system applications and can

be used with either an external reference clock or an on-chip

oscillator with external crystal. Both native rates and 15/14 rate

digital wrappers are supported by the ADN2807, without any

change of reference clock.

This device, together with a PIN diode and a TIA preamplifier,

can implement a highly integrated, low cost, low power, fiber

optic receiver.

Loopback mode for high speed test data

Output squelch and bypass features

Single-supply operation: 3.3 V

Low power: 540 mW typical

The receiver front end signal detect circuit indicates when the

input signal level has fallen below a user adjustable threshold.

The signal detect circuit has hysteresis to prevent chatter at the

output.

7 mm × 7 mm, 48-lead LFCSP

APPLICATIONS

SONET OC-3/-12, SDH STM-1/-4 and, 15/14 FEC rates

WDM transponders

The ADN2807 is available in a compact 7 mm × 7 mm 48-lead

chip-scale package (LFCSP).

Regenerators/repeaters

Test equipment

Passive optical networks

FUNCTIONAL BLOCK DIAGRAM

SLICEP/N

VCC

VEE

LOL

CF1

CF2

ADN2807

LOOP

FILTER

REFSEL[0..1]

NIN

REFCLKP/N

XO1

FREQUENCY

LOCK

DETECTOR

PHASE

SHIFTER

LOOP

FILTER

PHASE

DET.

QUANTIZER

VCO

XTAL

OSC

XO2

FRACTIONAL

DIVIDER

VREF

REFSEL

LEVEL

DATA

DIVIDER

DETECT

RETIMING

1/2/4/16

THRADJ

SDOUT

DATAOUTP/N

CLKOUTP/N

SEL[0..2]

Figure 1.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.326.8703

www.analog.com

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