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ADN2807ACP

更新时间: 2024-01-05 22:34:59
品牌 Logo 应用领域
亚德诺 - ADI 放大器时钟
页数 文件大小 规格书
20页 354K
描述
155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp

ADN2807ACP 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:LFCSP-48针数:48
Reach Compliance Code:compliantECCN代码:5A991.B.3
HTS代码:8542.39.00.01风险等级:5.28
应用程序:SONET;SDHJESD-30 代码:S-XQCC-N48
JESD-609代码:e3长度:7 mm
湿度敏感等级:3功能数量:1
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LCC48,.27SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:1 mm
子类别:ATM/SONET/SDH ICs最大压摆率:0.215 mA
标称供电电压:3.3 V表面贴装:YES
技术:BIPOLAR电信集成电路类型:ATM/SONET/SDH CLOCK RECOVERY CIRCUIT
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:7 mm

ADN2807ACP 数据手册

 浏览型号ADN2807ACP的Datasheet PDF文件第3页浏览型号ADN2807ACP的Datasheet PDF文件第4页浏览型号ADN2807ACP的Datasheet PDF文件第5页浏览型号ADN2807ACP的Datasheet PDF文件第7页浏览型号ADN2807ACP的Datasheet PDF文件第8页浏览型号ADN2807ACP的Datasheet PDF文件第9页 
ADN2807  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
THRADJ  
VCC  
1
2
3
4
5
6
7
8
9
36VCC  
35VCC  
34VEE  
33VEE  
32 SEL0  
31 NC  
30 SEL1  
29VEE  
28VCC  
27VEE  
26VCC  
25 CF2  
PIN 1  
INDICATOR  
VEE  
VREF  
PIN  
NIN  
SLICEP  
SLICEN  
VEE  
LOL 10  
XO1 11  
XO2 12  
ADN2807  
TOPVIEW  
Figure 2. Pin Configuration  
Table 3. Pin Function Descriptions  
Pin No.  
1
2, 26, 28, Pad  
Mnemonic  
THRADJ  
VCC  
Type1 Description  
AI  
P
LOS Threshold Setting Resistor.  
Analog Supply.  
3, 9, 16, 19,  
VEE  
P
Ground.  
22, 27, 29, 33,  
34, 42, 43, 46  
4
5
VREF  
PIN  
AO  
AI  
Internal VREF Voltage. Decouple to GND with a 0.1 µF capacitor.  
Differential Data Input.  
6
NIN  
AI  
Differential Data Input.  
7
8
SLICEP  
SLICEN  
LOL  
XO1  
XO2  
REFCLKN  
REFCLKP  
REFSEL  
TDINP  
TDINN  
VCC  
AI  
AI  
DO  
AO  
AO  
DI  
DI  
DI  
AI  
AI  
P
AO  
DI  
DI  
AO  
DI  
Differential Slice Level Adjust Input.  
Differential Slice Level Adjust Input.  
Loss-of-Lock Indicator. LVTTL active high.  
Crystal Oscillator.  
Crystal Oscillator.  
Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS (LVPECL, LVDS only at 155.52 MHz).  
Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS (LVPECL, LVDS only at 155.52 MHz).  
Reference Source Select. 0 = on-chip oscillator with external crystal. 1 = external clock source, LVTTL.  
Differential Test Data Input. CML.  
Differential Test Data Input. CML.  
Digital Supply.  
10  
11  
12  
13  
14  
15  
17  
18  
20, 47  
21  
23  
24  
25  
30  
31  
32  
35, 36  
37  
38  
39  
40  
41  
44  
45  
48  
CF1  
Frequency Loop Capacitor.  
REFSEL1  
REFSEL0  
CF2  
SEL1  
NC  
Reference Frequency Select (See Table 6) LVTTL.  
Reference Frequency Select (See Table 6) LVTTL.  
Frequency Loop Capacitor.  
Data Rate Select (See Table 5) LVTTL.  
No Connect.  
SEL0  
VCC  
DI  
P
Data Rate Select (See Table 5) LVTTL.  
Output Driver Supply.  
DATAOUTN  
DATAOUTP  
SQUELCH  
CLKOUTN  
CLKOUTP  
BYPASS  
SDOUT  
LOOPEN  
DO  
DO  
DI  
DO  
DO  
DI  
Differential Retimed Data Output. CML.  
Differential Retimed Data Output. CML.  
Disable Clock and Data Outputs. Active high. LVTTL.  
Differential Recovered Clock Output. CML.  
Differential Recovered Clock Output. CML.  
Bypass CDR Mode. Active high. LVTTL.  
Loss-of-Signal Detect Output. Active high. LVTTL.  
Enable Test Data Inputs. Active high. LVTTL.  
DO  
DI  
1Type: P = Power, AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output  
Rev. A | Page 6 of 20  
 
 

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