Datasheet > ADN2807ACP

ADN2807ACP

更新时间： 2024-01-05 06:38:50

品牌	Logo	应用领域
亚德诺 - ADI		放大器时钟
页数	文件大小	规格书
20页	354K
描述
155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp

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中文翻译

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技术参数
数据手册

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ADN2807ACP 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	LFCSP-48	针数：	48
Reach Compliance Code：	compliant	ECCN代码：	5A991.B.3
HTS代码：	8542.39.00.01	风险等级：	5.28
应用程序：	SONET;SDH	JESD-30 代码：	S-XQCC-N48
JESD-609代码：	e3	长度：	7 mm
湿度敏感等级：	3	功能数量：	1
端子数量：	48	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装等效代码：	LCC48,.27SQ,20
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	电源：	3.3 V
认证状态：	Not Qualified	座面最大高度：	1 mm
子类别：	ATM/SONET/SDH ICs	最大压摆率：	0.215 mA
标称供电电压：	3.3 V	表面贴装：	YES
技术：	BIPOLAR	电信集成电路类型：	ATM/SONET/SDH CLOCK RECOVERY CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	7 mm

ADN2807ACP 数据手册

ADN2807

DEFINITION OF TERMS

MAXIMUM, MINIMUM, AND TYPICAL

SPECIFICATIONS

SINGLE-ENDED VS. DIFFERENTIAL

AC coupling is typically used to drive the inputs to the

quantizer. The inputs are internally dc-biased to a common-

mode potential of ~0.6 V. Driving the ADN2807 single-ended

and observing the quantizer input with an oscilloscope probe at

the point indicated in Figure 9 shows a binary signal with

average value equal to the common-mode potential and

instantaneous values both above and below the average value. It

is convenient to measure the peak-to-peak amplitude of this

signal and call the minimum required value the quantizer

sensitivity. Referring to Figure 8, since both positive and

negative offsets need to be accommodated, the sensitivity is

twice the overdrive.

Specifications for every parameter are derived from statistical

analyses of data taken on multiple devices from multiple wafer

lots. Typical specifications are the mean of the distribution of

the data for that parameter. If a parameter has a maximum (or a

minimum) value, that value is calculated by adding to (or

subtracting from) the mean six times the standard deviation of

the distribution. This procedure is intended to tolerate pro-

duction variations. If the mean shifts by 1.5 standard deviations,

the remaining 4.5 standard deviations still provide a failure rate

of only 3.4 parts per million. For all tested parameters, the test

limits are guardbanded to account for tester variation, and

therefore guarantee that no device is shipped outside of data

sheet specifications.

10mV p-p

VREF

INPUT SENSITIVITY AND INPUT OVERDRIVE

SCOPE

PROBE

ADN2807

Sensitivity and overdrive specifications for the quantizer involve

offset voltage, gain, and noise. The relationship between the

logic output of the quantizer and the analog voltage input is

shown in Figure 8. For sufficiently large positive input voltage,

the output is always Logic 1; similarly for negative inputs, the

output is always Logic 0. However, the transitions between

output Logic Levels 1 and 0 are not at precisely defined input

voltage levels, but occur over a range of input voltages. Within

this zone of confusion, the output may be either 1 or 0, or it may

even fail to attain a valid logic state. The width of this zone is

determined by the input voltage noise of the quantizer. The

center of the zone of confusion is the quantizer input offset

voltage. Input overdrive is the magnitude of signal required to

guarantee a correct logic level with a 1 × 10^–10confidence level.

QUANTIZER

50Ω 50Ω

VREF

Figure 9. Single-Ended Sensitivity Measurement

5mV p-p

VREF

OUTPUT

SCOPE

PROBE

ADN2807

NOISE

QUANTIZER

NIN

50Ω 50Ω

VREF

INPUT (V p-p)

OFFSET

OVERDRIVE

SENSITIVITY

(2× OVERDRIVE)

Figure 10. Differential Sensitivity Measurement

Figure 8. Input Sensitivity and Input Overdrive

Driving the ADN2807 differentially (Figure 10), sensitivity

seems to improve by observing the quantizer input with an

oscilloscope probe. This is an illusion caused by the use of a

single-ended probe. A 5 mV p-p signal appears to drive the

ADN2807 quantizer. However, the single-ended probe measures

only half the signal. The true quantizer input signal is twice this

value since the other quantizer input is complementary to the

signal being observed.

Rev. A | Page 8 of 20

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与ADN2807ACP相关器件

型号	品牌	获取价格	描述	数据表
ADN2807ACP-RL	ADI	获取价格	155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp
ADN2809	ADI	获取价格	Multi-Rate to 2.7Gbps Clock and Data Recovery IC with Limiting Amplifier
ADN2809XCP	ADI	获取价格	Multi-Rate to 2.7Gbps Clock and Data Recovery IC with Limiting Amplifier
ADN2809XCP-RL	ADI	获取价格	Multi-Rate to 2.7Gbps Clock and Data Recovery IC with Limiting Amplifier
ADN2811	ADI	获取价格	OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp
ADN2811ACP-CML	ADI	获取价格	OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp
ADN2811ACP-CML-RL	ADI	获取价格	OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp
ADN2812	ADI	获取价格	Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting
ADN2812ACP	ADI	获取价格	Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting
ADN2812ACP-RL	ADI	获取价格	Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting

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