ADM1067ASU-REEL

更新时间： 2024-02-09 17:47:07

品牌	Logo	应用领域
亚德诺 - ADI		转换器数模转换器
页数	文件大小	规格书
32页	649K
描述
Super Sequencer with Open-Loop Margining DACs

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数据手册

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ADM1067ASU-REEL 数据手册

ADM1067

Pin Number

LFCSP¹TQFP

Mnemonic

Description

MDN

Digital Input. Forces DACs to their highest value, causing the voltage at the feedback node to rise.

This is compensated for by a decrease in the supply output voltage, thus margining down.

VDDCAP

Device Supply Voltage. Linearly regulated from the highest of the VPn, VH pins to a typical of 4.75 V.

Note that the capacitor must be connected between this pin and GND. A 10 μF capacitor is

recommended for this purpose.

GND²

Supply Ground.

¹Note that the LFCSP has an exposed pad on the bottom. This pad is a no connect (NC). If possible, this pad should be soldered to the board for improved mechanical stability.

²In a typical application, all ground pins are connected together.

Rev. B | Page 8 of 32

1...5 6 789 10 11...32

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