ADM1067
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
40 39 38 37 36 35 34 33 32 31
NC
VX1
VX2
VX3
VX4
VX5
VP1
VP2
VP3
1
2
3
4
5
6
7
8
9
36 NC
PIN 1
INDICATOR
VX1
VX2
VX3
VX4
VX5
VP1
VP2
VP3
VP4
1
2
3
4
5
6
7
8
9
30 PDO1
29 PDO2
28 PDO3
27 PDO4
26 PDO5
25 PDO6
24 PDO7
23 PDO8
22 PDO9
21 PDO10
35 PDO1
34 PDO2
33 PDO3
32 PDO4
31 PDO5
30 PDO6
29 PDO7
28 PDO8
27 PDO9
26 PDO10
25 NC
PIN 1
INDICATOR
ADM1067
ADM1067
TOP VIEW
TOP VIEW
(Not to Scale)
(Not to Scale)
VP4 10
VH 11
NC 12
VH 10
11 12 13 14 15 16 17 18 19 20
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
NC = NO CONNECT
Figure 3. LFCSP Pin Configuration
Figure 4. TQFP Pin Configuration
Table 2. Pin Function Descriptions
Pin Number
LFCSP1 TQFP
Mnemonic
Description
No Connection.
13
1, 12, 13, 16, NC
24, 25, 36,
37, 48
1 to 5
6 to 9
2 to 6
VX1 to VX5
(VXn)
VP1 to VP4
(VPn)
High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to
1.375 V. Alternatively, these pins can be used as general-purpose digital inputs.
Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the input
attenuation on a potential divider connected to these pins, the output of which connects to a
supply fault detector. These pins allow thresholds from 2.5 V to 6.0 V, 1.25 V to 3.00 V, and 0.573 V
to 1.375 V.
7 to 10
10
11
VH
High Voltage Input to Supply Fault Detectors. Three input ranges can be set by altering the input
attenuation on a potential divider connected to this pin, the output of which connects to a supply
fault detector. This pin allows thresholds from 6.0 V to 14.4 V and 2.5 V to 6.0 V.
Ground Return for Input Attenuators.
Ground Return for On-Chip Reference Circuits.
11
12
14
14
15
17
AGND2
REFGND2
REFOUT
2.048 V Reference Output. Note that the capacitor must be connected between this pin and
REFGND. A 10 μF capacitor is recommended for this purpose.
15 to 20 18 to 23
21 to 30 26 to 35
DAC1 to
DAC6
PDO10 to
PDO1
Voltage Output DACs. These pins default to high impedance at power-up.
Programmable Output Drivers.
31
32
38
39
PDOGND2
VCCP
Ground Return for Output Drivers.
Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between this pin
and GND. A 10 μF capacitor is recommended for this purpose.
33
34
35
36
37
40
41
42
43
44
A0
A1
SCL
SDA
MUP
Logic Input. This pin sets the seventh bit of the SMBus interface address.
Logic Input. This pin sets the sixth bit of the SMBus interface address.
SMBus Clock Pin. Open-drain output requires external resistive pull-up.
SMBus Data I/O Pin. Open-drain output requires external resistive pull-up.
Digital Input. Forces DACs to their lowest value, causing the voltage at the feedback node to drop.
This is compensated for by an increase in the supply output voltage, thus margining up.
Rev. B | Page 7 of 32
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