ADM1067ASU-REEL

更新时间： 2024-01-28 19:12:17

品牌	Logo	应用领域
亚德诺 - ADI		转换器数模转换器
页数	文件大小	规格书
32页	649K
描述
Super Sequencer with Open-Loop Margining DACs

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数据手册

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ADM1067ASU-REEL 数据手册

ADM1067

Parameter

Min

Typ

Max

Unit Test Conditions/Comments

Gain Error

Maximum Load Current (Source)

Maximum Load Current (Sink)

Maximum Load Capacitance

Settling Time into 50 pF Load

Load Regulation

100

μA

μs

2.5

Per mA

PSRR

100 mV step in 20 ns with 50 pF load

REFERENCE OUTPUT

Reference Output Voltage

Load Regulation

2.043 2.048

2.053

No load

μF

−0.25

0.25

Sourcing current, I_DACnMAX= −100 μA

Sinking current, I_DACnMAX= 100 μA

Capacitor required for decoupling, stability

Minimum Load Capacitance

PSRR

PROGRAMMABLE DRIVER OUTPUTS

High Voltage (Charge Pump) Mode

(PDO1 to PDO6)

Output Impedance

V_OH

500

12.5

kΩ

10.5

13.5

I_OH= 0

I_OH= 1 μA

2 V < V_OH< 7 V

I_OUTAVG

μA

Standard (Digital Output) Mode

(PDO1 to PDO10)

V_OH

2.4

V_PU(pull-up to VDDCAP or VPn) = 2.7 V, I_OH= 0.5 mA

V_PUto VPn = 6.0 V, I_OH= 0 mA

V_PU≤ 2.7 V, I_OH= 0.5 mA

4.5

V_PU

0.3

−

V_OL

I_OL

I_SINK

R_PULL-UP

0.50

I_OL= 20 mA

kΩ

Maximum sink current per PDO pin

Maximum total sink for all PDOs

Internal pull-up

Current load on any VPn pull-ups, that is, total source current

available through any number of PDO pull-up switches

configured onto any one

I_SOURCE(VPn)²

Three-State Output Leakage Current

Oscillator Frequency

110

μA

kHz

V_PDO= 14.4 V

All on-chip time delays derived from this clock

2.0

−1

100

DIGITAL INPUTS (VXn, A0, A1, MUP, MDN)

Input High Voltage, V_IH

Input Low Voltage, V_IL

Input High Current, I_IH

Input Low Current, I_IL

Input Capacitance

Programmable Pull-Down Current,

I_PULL-DOWN

μA

Maximum V_IN= 5.5 V

V_IN= 5.5 V

0.8

V_IN= 0

VDDCAP = 4.75, T_A= 25°C, if known logic state is required

SERIAL BUS DIGITAL INPUTS (SDA, SCL)

Input High Voltage, V_IH

2.0

Input Low Voltage, V_IL

0.8

0.4

Output Low Voltage, V_OL

I_OUT= −3.0 mA

SERIAL BUS TIMING

Clock Frequency, f_SCLK

Bus Free Time, t_BUF

Start Setup Time, t_SU;STA

Start Hold Time, t_HD;STA

SCL Low Time, t_LOW

400

kHz

μs

4.7

Rev. B | Page 5 of 32

1 2 3 456 7 8...32

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