ADM1067ASU-REEL

更新时间： 2024-02-13 03:04:04

品牌	Logo	应用领域
亚德诺 - ADI		转换器数模转换器
页数	文件大小	规格书
32页	649K
描述
Super Sequencer with Open-Loop Margining DACs

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ADM1067ASU-REEL 数据手册

ADM1067

(continued from Page 1)

GENERAL DESCRIPTION

Supply margining can be performed with a minimum of

external components. The margining capability can be used for

in-circuit testing of a board during production (for example, to

verify the board functionality at −5% of nominal supplies). It

can also be used dynamically to accurately control the output

voltage of a dc-to-dc converter.

for driving the gate of an N-channel FET that can be placed in

the path of a supply.

The logical core of the device is a sequencing engine. This state-

machine-based construction provides up to 63 different states.

This design enables very flexible sequencing of the outputs,

based on the condition of the inputs.

The device provides up to 10 programmable inputs for

monitoring under, over, or out-of-window faults on up to 10

supplies. In addition, 10 programmable outputs can be used as

logic enables. Six of them can also provide up to a 12 V output

The device is controlled via configuration data that can be

programmed into an EEPROM. The whole configuration can

be programmed using an intuitive GUI-based software package

provided by Analog Devices, Inc.

10µF

REFOUT

REFGND SDA SCL A1

OSC

SMBus

INTERFACE

DEVICE

CONTROLLER

VREF

EEPROM

GPI SIGNAL

CONFIGURABLE

O/P DRIVER

(HV)

ADM1067

CONDITIONING

PDO1

PDO2

PDO3

PDO4

SFD

VX1

VX2

VX3

VX4

GPI SIGNAL

CONDITIONING

CONFIGURABLE

O/P DRIVER

(HV)

SEQUENCING

ENGINE

VX5

VP1

SFD

SELECTABLE

ATTENUATOR

CONFIGURABLE

O/P DRIVER

(LV)

PDO5

PDO6

PDO7

PDO8

PDO9

PDO10

VP2

VP3

VP4

SELECTABLE

ATTENUATOR

SFD

CONFIGURABLE

O/P DRIVER

(LV)

AGND

VDDCAP

VDD

ARBITRATOR

10µF

MDN

MUP

PDOGND

GND

DAC

OUT

DAC

OUT

VCCP

10µF

REG 5.25V

CHARGE PUMP

DAC1

DAC2

DAC3

DAC4

DAC5

DAC6

Figure 2. Detailed Block Diagram

Rev. B | Page 3 of 32

1 234 5 6 7...32

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