ADL5330
The results show that up to a total output power of +8 dBm,
CDMA2000 TRANSMIT APPLICATION
ACPR remains in compliance with the standard (<−45 dBc @
750 kHz and <−60 dBc @ 1.98 MHz). At low output power
levels, ACPR at 1.98 MHz carrier offset degrades as the noise
floor of the ADL5330 becomes the dominant contributor to
measured ACPR. Measured noise at 4 MHz carrier offset begins
to increase sharply above 0 dBm output power. This increase is
not due to noise but results from increased carrier-induced
distortion. As output power drops below 0 dBm total, the noise
floor drops towards −85 dBm.
To test the compliance to the CDMA2000 base station standard,
an 880 MHz, three-carrier CDMA2000 test model signal
(forward pilot, sync, paging, and six traffic, as per 3GPP2
C.S0010-B, Table 6.5.2.1) was applied to the ADL5330. A cavity-
tuned filter with a 4.6 MHz pass band was used to reduce noise
from the signal source being applied to the device.
Figure 46 shows the spectrum of the output signal under
nominal conditions. Total POUT of the three-carrier signal is
equal to 0.46 dBm and VGAIN = 1.4 V. Adjacent and alternate
channel power ratio is measured in a 30 kHz bandwidth at
750 kHz and 1.98 MHz carrier offset, respectively.
With a fixed input power of −23 dBm, the output power was
again swept by exercising the gain control input. VGAIN was
swept from 0 V to 1.4 V. The resulting total output power,
ACPR, and noise floor are shown in Figure 48.
MARKER 1 [T1]
RBW 30kHz
RF ATT 10dB
REF LVL
–10dBm
–18.55dBm VBW 300kHz MIXER –10dBm
UNIT dBm
10
–30
–40
–50
–60
–70
–80
–90
–100
880.00000000MHz SWT 200ms
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0.4 dB OFFSET
1 [T1]
–18.55dBm
880MHz
1
A
0
CH PWR
ACP Up
0.46dBm
–65.13dB
–64.40dB
–89.05dB
–83.68dB
–80.72dB
–81.24dB
OUTPUT POWER
ACP Low
ALT1 Up
ALT1 Low
ALT2 Up
ALT2 Low
–10
–20
–30
–40
–50
–60
1 AVG
1RM
EXT
ACPR 750kHz OFFSET
ACPR 1.98MHz OFFSET
C0
C0
CL3
CL3
CL2
CL2
CL1
CL1
CU1
CU1
CU2
CU2
NOISE 4MHz OFFSET
0.8 1.0
(V)
CU3
CU3
0
0.2
0.4
0.6
V
1.2
1.4
GAIN
CENTER 880MHz
1.5MHz/
SPAN 15MHz
Figure 48. Total Output Power and ACPR vs. VGAIN, 880 MHz Three-Carrier
CDMA2000 Test Model at −23 dBm Total Input Power; ACPR Measured in
30 kHz Bandwidth at 750 kHz and 1.98 MHz Carrier Offset
Figure 46. 880 MHz Output Spectrum, Three-Carrier CDMA2000 Test Model
at −23 dBm Total Input Power, VGAIN = 1.4 V, ACPR Measured at 750 kHz and
1.98 MHz Carrier Offset, Input Signal Filtered Using a Cavity Tuned Filter
(Pass Band = 4.6 MHz)
Above VGAIN = 0.4 V, the ACPR is still in compliance with the
standard. As the gain control input drops below 1.0 V, the noise
floor drops below −90 dBm.
In testing, by holding the gain control voltage steady at 1.4 V,
input power was swept. Figure 47 shows ACPR and noise floor
vs. total output power. Noise floor is measured at 1 MHz
bandwidth at 4 MHz carrier offset.
SOLDERING INFORMATION
On the underside of the chip scale package, there is an exposed
compressed paddle. This paddle is internally connected to the
chip’s ground. Solder the paddle to the low impedance ground
plane on the printed circuit board to ensure specified electrical
performance and to provide thermal relief. It is also
recommended that the ground planes on all layers under the
paddle be stitched together with vias to reduce thermal
impedance.
–30
–0
–40
–10
–20
–30
–40
–50
–60
–70
–80
–90
–50
–60
ACPR 750kHz OFFSET
–70
–80
–90
ACPR 1.98MHz OFFSET
NOISE 4MHz OFFSET
–100
–110
–120
–30
–25
–20
–15
–10
–5
0
5
10
15
TOTAL OUTPUT POWER (dBm)
Figure 47. ACPR vs. Total Output Power, 880 MHz Three-Carrier CDMA2000
Test Model; VGAIN = 1.4 V (Fixed), ACPR Measured in 30 kHz Bandwidth at
750 kHz and 1.98 MHz Carrier Offset
Rev. A | Page 19 of 24
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