ADL5306
The use of a negative supply, VN, allows the summing node to be
placed at ground level whenever the input transistor (Q1 in
Figure 1) has a sufficiently negative bias on its emitter. When
VN = –0.5 V, the VCE of Q1 and Q2 will be the same value as in
the default case when VSUM is grounded. This bias need not be
accurate, and a poorly defined source can be used. However, the
source must be able to support the quiescent current as well as
the INPT and IREF signal current. For example, it may be
convenient to utilize a forward-biased junction voltage of about
0.7 V or a Schottky barrier voltage of a little over 0.5 V. With the
summing node at ground, the ADL5306 may now be used as a
voltage-input log amp, at either the numerator input INPT or
the denominator input IREF by inserting a suitably scaled
resistor from the voltage source to the relevant pin. The overall
accuracy for small input voltages is limited by the voltage offset
at the inputs of the JFET op amps.
VREF
IREF
VNEG
VPOS
VOUT
KEITHLEY 236
KEITHLEY 236
ADL5306
BFIN
CHARACTERIZATION
BOARD
VLOG
INPT
VSUM
RIBBON
CABLE
TRIAX CONNECTORS
(SIGNAL – INPT AND IREF
GUARD – VSUM
SHIELD – GROUND)
DC MATRIX / DC SUPPLIES / DMM
03727-0-024
Figure 24. Primary Characterization Setup
The primary characterization setup shown in Figure 24 is used
to measure VREF, the static (dc) performance, logarithmic
conformance, slope and intercept, the voltages appearing at Pins
VSUM, INPT, and IREF, and the buffer offset and VREF drift
with temperature. In some cases, a fixed resistor between Pins
VREF and IREF was used in place of a precision current source.
For the dynamic tests, including noise and bandwidth
measurements, more specialized setups are required. This
includes close attention to the input stabilizing networks; for
example, to ensure stable operation over the full current range
of IREF and temperature extremes, filter components C1 = 4.7 nF
and R13 = 2 kΩ are used at Pin IREF to ground.
The use of a negative supply also allows the output to swing
below ground, thereby allowing the intercept to correspond to a
midrange value of IPD. However, the voltage VLOG remains
referenced to the ACOM pin, and while VLOG does not swing
negative for default operating conditions, it is free to do so.
Thus, adding a resistor from VLOG to the negative supply
lowers all values of VLOG, which raises the intercept. The
disadvantage of this method is that the slope is reduced by the
shunting of the external resistor, and the poorly defined ratio of
on-chip and off-chip resistance causes errors in both the slope
and intercept. A more accurate method for repositioning the
intercept follows.
HP3577A
NETWORK ANALYZER
OUTPUT INPUT R INPUT A INPUT B
CHARACTERIZATION METHODS
During the characterization of the ADL5306, the device was
treated as a precision current-input logarithmic converter,
because it is impractical to generate accurate photocurrents by
illuminating a photodiode. The test currents were generated by
using either a well-calibrated current source, such as the
Keithley 236, or a high value resistor from a voltage source to
the input pin. Great care is needed when using very small input
currents. For example, the triax output connection from the
current generator was used with the guard tied to VSUM. The
input trace on the PC board was guarded by connecting
adjacent traces to VSUM.
16
15
14
13
COMM COMM COMM COMM
B
A
+INAD8138
EVALUATION
BOARD
VOUT
SCAL
BFIN
NC
12
11
10
9
1
2
3
4
BNC-T
VREF
IREF
INPT
ADL5306
AD8138 PROVIDES DC OFFSET
VLOG
VSUM VNEG VNEG VPOS
5
6
7
8
+V
S
0.1µF
These measures are needed to minimize the risk of leakage
current paths. With 0.5 V as the nominal bias on the INPT pin,
a leakage-path resistance of 1 GΩ to ground would subtract
0.5 nA from the input, which amounts to a –0.44 dB error for a
10 nA source current. Additionally, the very high output
resistance at the input pins and the long cables commonly
needed during characterization allow 60 Hz and RF emissions
to introduce substantial measurement errors. Careful guarding
techniques are essential to reducing the pickup of these
spurious signals.
03727-0-025
Figure 25. Configuration for Buffer Amplifier Bandwidth Measurement
Figure 25 shows the configuration used to measure the buffer
amplifier bandwidth. The AD8138 evaluation board includes
provisions to offset VLOG at the buffer input, allowing
measurements over the full range of IPD using a single supply.
The network analyzer input impedances are set to 1 MΩ.
Rev. 0 | Page 12 of 16
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