ADL5306
GENERAL STRUCTURE
The ADL5306 addresses a wide variety of interfacing conditions
to meet the needs of fiber optic supervisory systems, and is
useful in many nonoptical applications. This section explains
the structure of this unique style of translinear log amp. The
simplified schematic in Figure 21 shows the key elements.
THEORY
The base-emitter voltage of a BJT (bipolar junction transistor)
can be expressed by the following equation, which immediately
shows its basic logarithmic nature:
V
BE = kT/q ln(IC / IS)
(1)
BIAS
GENERATOR
where:
IREF
PHOTODIODE
INPUT
V
V
BE1
BE2
TEMPERATURE
COMPENSATION
(SUBTRACT AND
DIVIDE BY T°K)
IC is the collector current
2.5V
VREF
IS is a scaling current, typically only 10–17
A
CURRENT
I
REF
80kΩ
0.5V
20kΩ
COMM
kT/q is the thermal voltage, proportional to absolute
temperature (PTAT), and is 25.85 mV at 300 K.
I
PD
VSUM
44µA/dec
INPT
0.5V
14.2kΩ 451Ω
IS is never precisely defined and exhibits an even stronger
temperature dependence, varying by a factor of roughly a
2.5V
VLOG
0.5V
Q1
billion between –35°C and +85°C. Thus, to make use of the BJT
as an accurate logarithmic element, both of these temperature-
dependencies must be eliminated.
V
V
Q2
BE2
6.69kΩ
BE1
COMM
03727-0-021
VNEG (NORMALLY GROUNDED)
The difference between the base-emitter voltages of a matched
pair of BJTs, one operating at the photodiode current IPD and
the other operating at a reference current IREF, can be written as
Figure 21. Simplified Schematic
The photodiode current IPD is received at Pin INPT. The voltage
at this node is essentially equal to the voltage on the two
adjacent guard pins, VSUM and IREF, due to the low offset
voltage of the JFET op amp. Transistor Q1 converts IPD to a
corresponding logarithmic voltage, as shown in Equation 1. A
finite positive value of VSUM is needed to bias the collector of Q1
for the usual case of a single-supply voltage. This is internally
set to 0.5 V, one fifth of the 2.5 V reference voltage appearing on
Pin VREF. The resistance at the VSUM pin is nominally 16 kΩ;
this voltage is not intended as a general bias source.
VBE1 – VBE2 = kT/q ln(IPD / IS) – kT/q ln(IREF / IS)
= ln(10) kT/q log10(IPD /IREF
)
(2)
= 59.5 mV log10(IPD /IREF) (T = 300 K)
The uncertain, temperature-dependent saturation current, IS,
that appears in Equation 1 has therefore been eliminated. To
eliminate the temperature variation of kT/q, this difference
voltage is processed by what is essentially an analog divider.
Effectively, it puts a variable under Equation 2. The output of
this process, which also involves a conversion from voltage
mode to current mode, is an intermediate, temperature-
corrected current:
The ADL5306 also supports the use of an optional negative
supply voltage, VN , at Pin VNEG. When VN is –0.5 V or more
negative, VSUM may be connected to ground; thus, INPT and
IREF assume this potential. This allows operation as a voltage-
input logarithmic converter by the inclusion of a series resistor
at either or both inputs. Note that the resistor setting, IREF, will
need to be adjusted to maintain the intercept value. It should
also be noted that the collector-emitter voltages of Q1 and Q2
are now the full VN, and effects due to self-heating will cause
errors at large input currents.
I
LOG = IY log10(IPD IREF
)
(3)
/
where IY is an accurate, temperature-stable scaling current that
determines the slope of the function (change in current per
decade). For the ADL5306, IY is 44 µA, resulting in a
temperature-independent slope of 44 µA/decade for all values
of IPD and IREF . This current is subsequently converted back to a
voltage-mode output, VLOG, scaled 200 mV/decade.
The input-dependent VBE1 of Q1 is compared with the reference
VBE2 of a second transistor, Q2, operating at IREF. This is
generated externally to a recommended value of 10 µA.
However, other values over a several-decade range can be used
with a slight degradation in law conformance (see Figure 8).
Rev. 0 | Page 9 of 16
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