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ADF4193BCPZ-RL7

更新时间： 2024-02-26 13:57:01

品牌	Logo	应用领域
亚德诺 - ADI		信号电路锁相环或频率合成电路信息通信管理
页数	文件大小	规格书
28页	595K
描述
Low Phase Noise, Fast Settling PLL Frequency Synthesizer

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技术参数
数据手册

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ADF4193BCPZ-RL7 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN, LCC32,.2SQ,20	针数：	32
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.67
Is Samacsys：	N	模拟集成电路 - 其他类型：	PLL FREQUENCY SYNTHESIZER
JESD-30 代码：	S-XQCC-N32	JESD-609代码：	e3
长度：	5 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	32
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装等效代码：	LCC32,.2SQ,20	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
电源：	3 V	认证状态：	Not Qualified
座面最大高度：	1 mm	子类别：	PLL or Frequency Synthesis Circuits
最大供电电流 (Isup)：	27 mA	最大供电电压 (Vsup)：	3.3 V
最小供电电压 (Vsup)：	2.7 V	标称供电电压 (Vsup)：	3 V
表面贴装：	YES	技术：	BICMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	5 mm	Base Number Matches：	1

ADF4193BCPZ-RL7 数据手册

ADF4193

ADSP-21xx Interface

INTERFACING

Figure 38 shows the interface between the ADF4193 and the

ADSP-21xx digital signal processor. The ADF4193 needs a

24-bit serial word for some writes. The easiest way to accom-

plish this using the ADSP-21xx family is to use the autobuffered

transmit mode of operation with alternate framing. This

provides a means for transmitting an entire block of serial data

before an interrupt is generated. Set up the word length for

eight bits and use three memory locations for each 24-bit word.

To program each 24-bit word, store the three 8-bit bytes, enable

the autobuffered mode, and then write to the transmit register

of the DSP. This last operation initiates the autobuffer transfer.

The ADF4193 has a simple SPI®-compatible serial interface for

writing to the device. CLK, DATA, and LE control the data

transfer. When LE goes high, the 24 bits that have been clocked

into the input register on each rising edge of CLK are latched

into the appropriate register. See Figure 2 for the timing

diagram and Table 5 for the register address table.

The maximum allowable serial clock rate is 33 MHz.

ADuC812 Interface

Figure 37 shows the interface between the ADF4193 and the

ADuC812 MicroConverter®. Because the ADuC812 is based on

an 8051 core, this interface can be used with any 8051-based

microcontroller. The MicroConverter is set up for SPI master

mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Some registers of the ADF4193

require a 24-bit programming word. This is accomplished by

writing three 8-bit bytes from the MicroConverter to the device.

When the third byte is written, the LE input should be brought

high to complete the transfer.

ADSP-21xx

ADF4193

SCLK

CLK

DATA

TFS

MUX

I/O FLAGS

OUT

(LOCK DETECT)

An I/O port line on the ADuC812 can also be used to detect

lock (MUX_OUTconfigured as lock detect and polled by the

port input).

Figure 38. ADSP-21xx to ADF4193 Interface

PCB DESIGN GUIDELINES FOR CHIP SCALE

PACKAGE

ADuC812

ADF4193

The lands on the chip scale package (CP-32-3) are rectangular.

The printed circuit board (PCB) pad for these should be

0.1 mm longer than the package land length and 0.05 mm wider

than the package land width. The land should be centered on

the pad. This ensures that the solder joint size is maximized.

The bottom of the chip scale package has a central thermal pad.

SCLOCK

CLK

MOSI

DATA

I/O PORTS

MUX

OUT

(LOCK DETECT)

The thermal pad on the PCB should be at least as large as the

exposed pad. On the PCB, there should be a clearance of at least

0.25 mm between the thermal pad and the inner edges of the

pad pattern. This ensures that shorting is avoided.

Figure 37. ADuC812 to ADF4193 Interface

Thermal vias can be used on the PCB thermal pad to improve

the thermal performance of the package. If vias are used, they

should be incorporated in the thermal pad at 1.2 mm pitch grid.

The via diameter should be between 0.3 mm and 0.33 mm, and

the via barrel should be plated with one ounce copper to plug

the via.

The user should connect the PCB thermal pad to A_GND

Rev. B | Page 27 of 28

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与ADF4193BCPZ-RL7相关器件

型号	品牌	描述	获取价格	数据表
ADF4196	ADI	Low Phase Noise, Fast Settling, 6 GHz	获取价格
ADF4196BCPZ	ADI	Low Phase Noise, Fast Settling, 6 GHz	获取价格
ADF4196BCPZ-RL7	ADI	Low Phase Noise, Fast Settling, 6 GHz	获取价格
ADF4206	ADI	Dual RF PLL Frequency Synthesizers	获取价格
ADF4206BCHIPS	ADI	IC PLL FREQUENCY SYNTHESIZER, 500 MHz, UUC, DIE, PLL or Frequency Synthesis Circuit	获取价格
ADF4206BRU	ADI	Dual RF PLL Frequency Synthesizers	获取价格

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