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ADF4193BCPZ-RL7 PDF预览

ADF4193BCPZ-RL7

更新时间: 2024-01-11 11:29:45
品牌 Logo 应用领域
亚德诺 - ADI 信号电路锁相环或频率合成电路信息通信管理
页数 文件大小 规格书
28页 595K
描述
Low Phase Noise, Fast Settling PLL Frequency Synthesizer

ADF4193BCPZ-RL7 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN, LCC32,.2SQ,20针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.67
Is Samacsys:N模拟集成电路 - 其他类型:PLL FREQUENCY SYNTHESIZER
JESD-30 代码:S-XQCC-N32JESD-609代码:e3
长度:5 mm湿度敏感等级:3
功能数量:1端子数量:32
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC32,.2SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:3 V认证状态:Not Qualified
座面最大高度:1 mm子类别:PLL or Frequency Synthesis Circuits
最大供电电流 (Isup):27 mA最大供电电压 (Vsup):3.3 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:5 mmBase Number Matches:1

ADF4193BCPZ-RL7 数据手册

 浏览型号ADF4193BCPZ-RL7的Datasheet PDF文件第22页浏览型号ADF4193BCPZ-RL7的Datasheet PDF文件第23页浏览型号ADF4193BCPZ-RL7的Datasheet PDF文件第24页浏览型号ADF4193BCPZ-RL7的Datasheet PDF文件第26页浏览型号ADF4193BCPZ-RL7的Datasheet PDF文件第27页浏览型号ADF4193BCPZ-RL7的Datasheet PDF文件第28页 
ADF4193  
APPLICATIONS  
LOCAL OSCILLATOR FOR A GSM BASE STATION  
Timer Values for Tx  
To comply with the GSM spectrum due to switching require-  
ments, the Tx synthesizer should not switch frequency until the  
PA output power has ramped down by at least 50 dB. If it takes  
10 μs to ramp down to this level, then only the last 20 μs of the  
30 μs guard period is available for the Tx synthesizer to lock to  
final frequency and phase.  
Figure 36 shows the ADF4193 being used with a VCO to  
produce the LO for a GSM1800 base station. For GSM, the  
REFIN signal can be any integer multiple of 13 MHz, but the  
main requirement is that the slew rate is at least 300 V/μs.  
The 5 dBm, 104 MHz input sine wave shown satisfies this  
requirement.  
In fast lock mode, the Tx loop BW is widened by a factor-of-8  
to 480 kHz, and therefore, the PLL achieves frequency lock for a  
jump across the entire band in <6 μs. After this, the PA power  
can start to ramp up again, and the loop BW can be restored to  
the final value. With the ICP timer = 28, the charge pump  
current reduction begins at ~8.6 μs. When SW1, SW2, and SW3  
timers = 35, the current reaches its final value before the loop  
filter switches open at ~10.8 μs.  
Recommended parameters for the various GSM/PCS/DCS  
synthesizers are given in Table 9.  
Table 9. Recommended Setup Parameters  
GSM900  
DCS1800/PCS1900  
Parameter  
Loop BW  
PFD (MHz)  
MOD  
Dither  
Prescaler  
ICP Timer  
Tx  
Rx  
Tx  
Rx  
60 kHz  
13  
65  
Off  
4/5  
28  
40 kHz  
26  
130  
Off  
4/5  
78  
60 kHz  
13  
65  
Off  
8/9  
28  
40 kHz  
13  
65  
Off  
8/9  
38  
With these timer values, the phase disturbance created when  
the bandwidth is reduced settles back to its final value by 20 μs,  
in time for the start of the active part of the GSM burst. If faster  
phase settling is desired with the 60 kHz BW setting, then the timer  
values can be reduced further but should not be brought less than  
the 6 μs it takes to achieve frequency lock in wide BW mode.  
SW1, SW2,  
35  
85  
35  
45  
SW3 Timers  
VCO KV  
18 MHz/V 18 MHz/V 38 MHz/V 38 MHz/V  
Timer Values for Rx  
Loop BW and PFD Frequency  
The 40 kHz Rx loop BW is increased by a factor-of-8 to  
approximately 320 kHz during fast lock. With the Rx timer  
values shown, the BW is reduced after ~12 μs, which allows  
sufficient time for the phase disturbance to settle back before  
the start of the active part of the Rx time slot at 30 μs. As in the  
Tx case, faster Rx settling can be achieved by reducing these  
timer values, their lower limit being determined by the time it  
takes to achieve frequency lock in wide BW mode. In addition,  
the PCS and DCS Rx synthesizers have relaxed 800 kHz blocker  
specifications and thus can tolerate a wider loop BW, which  
allows correspondingly faster settling.  
A 60 kHz loop BW is narrow enough to attenuate the PLL phase  
noise and spurs to the required level for a Tx low. A 40 kHz BW  
is necessary to meet the GSM900 Rx synthesizers particularly  
tough phase noise and spur requirements at 800 kHz offsets.  
To get the lowest spur levels at 800 kHz offsets for Rx, the Σ-Δ  
modulator should be run at the highest oversampling rate  
possible. Therefore, for GSM900 Rx, a 26 MHz PFD frequency  
is chosen and MOD = 130 is required for 200 kHz steps.  
Because this value of MOD is divisible by two, certain FRAC  
channels have a 100 kHz fractional spur. This is attenuated by  
the 40 kHz loop filter and therefore is not a concern. However,  
the 60 kHz loop filter recommended for Tx has a closed-loop  
response that peaks close to 100 kHz. Therefore, a 13 MHz PFD  
with MOD = 65, which avoids the 100 kHz spur, is the best  
choice for a Tx synthesizer.  
VCO KV  
In general, the VCO gain, KV, should be set as low as possible to  
minimize the reference and integer boundary spur levels that arise  
due to feedthrough mechanisms. When deciding on the optimum  
VCO KV, a good choice is to allow 2 V to tune across the desired  
band, centered on the available tuning range. With VP3 regulated  
to 5.5 V 100 mV, the tuning range available is 2.8 V.  
Dither  
Dither off should be selected for the lowest rms phase error.  
Prescaler  
Loop Filter Components  
The 8/9 prescaler should be selected for the PCS and DCS  
bands. The 4/5 prescaler allows an N divider range low enough  
to cover the GSM900 Tx and Rx bands with either a 13 MHz or  
26 MHz PFD frequency.  
It is important for good settling performance that capacitors  
with low dielectric absorption are used in the loop filter.  
Ceramic NPO COG capacitors are a good choice for this  
application. A 2ꢀ tolerance is recommended for loop filter  
capacitors and 1ꢀ for resistors. A 10ꢀ tolerance is adequate  
for the inductor, L1.  
Rev. B | Page 25 of 28  
 
 
 

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