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ADF4207BCHIPS

更新时间: 2024-12-01 21:14:31
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
5页 104K
描述
IC PLL FREQUENCY SYNTHESIZER, 1100 MHz, UUC, DIE, PLL or Frequency Synthesis Circuit

ADF4207BCHIPS 数据手册

 浏览型号ADF4207BCHIPS的Datasheet PDF文件第2页浏览型号ADF4207BCHIPS的Datasheet PDF文件第3页浏览型号ADF4207BCHIPS的Datasheet PDF文件第4页浏览型号ADF4207BCHIPS的Datasheet PDF文件第5页 
a
Preliminary Technical Data  
Dual PLL Frequency Synthesizer  
ADF4206/ADF4207/ADF4208  
FEATURES  
GE NE RAL D E SC RIP T IO N  
ADF4206:  
ADF4207:  
ADF4208:  
+2.7 V to +5.5 V Pow er Supply  
Selectable Charge Pum p Currents  
Selectable Dual Modulus Prescaler  
3-Wire Serial Interface  
500MHz/ 500MHz  
1.1GHz/ 1.1GHz  
2.0GHz/ 1.1GHz  
T he ADF4206/ADF4207/ADF4208 is a dual frequency  
synthesizer which can be used to implement local oscil-  
lators in the up-conversion and down-conversion sec-  
tions of wireless receivers and transmitters. T hey consist  
of a low-noise digital PFD (Phase Frequency Detector),  
a precision charge pump, a programmable reference  
divider, programmable A and B counters and a dual-  
modulus prescaler (P/P+1). T he A (6-bit) and B (11-  
bit) counters, in conjunction with the dual modulus  
prescaler (P/P+1), implement an N divider (N= BP+A).  
In addition, the 14-bit reference counter (R Counter),  
allows selectable REFIN frequencies at the PFD input.  
A complete PLL (Phase-Locked Loop) can be imple-  
mented if the synthesizers are used with an external loop  
filter and VCO's (Voltage Controlled Oscillators)  
Pow er Dow n Mode  
APPLICATIONS  
Portable Wireless Com m unications (PCS/ PCN, Cordless)  
Cordless and Cellular Telephone System s  
Wireless Local Area Netw orks (WLANs)  
Cable TV Tuners (CATV)  
Pagers  
Control of all the on-chip registers is via a simple 3-wire  
interface.  
T he devices operate with a 3V ( ± 10%) or 5V( ± 10%)  
power supply and can be powered down when not in  
use.  
FUNCTIO NAL BLO CK D IAGRAM  
V
1
V
2
V
1
V 2  
P
DD  
DD  
P
ADF4206/ADF4207/ADF4208  
SWALLOW  
CO NTROL  
RF2IN  
A
17-B IT RF  
2
+
-
R F  
2
N-C OUNTER  
PRESC ALE  
R
RF2IN  
B
CH ARGE  
PUMP  
CP  
RF2  
PHASE  
CO MPAR ATOR  
14-BIT RF 2  
R-C OUNT ER  
IF  
LOCK  
DETECT  
OSCIN  
OSCILLATOR  
OSCOUT  
OUTPUT  
M UX  
MUXOUT  
CLOCK  
DATA  
LE  
22-BIT  
DAT A  
REGISTER  
SDOUT  
RF  
LOCK  
DETECT  
+
17-BIT R F  
N-COUNTER  
1
RF1INA  
RF1INB  
R F  
1
PRESC ALE  
R
-
CH ARGE  
PUMP  
CP  
RF1  
14-BIT RF  
1
R-C OUNT ER  
PHASE  
CO MPAR ATOR  
SWALL OW  
CONTRO L  
DGND  
AGND  
DGND  
AGND  
RF2 RF2  
RF1  
RF1  
REV.PrD 07/99  
© Analog Devices, Inc., 1999  
Inform ation furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assum ed by Analog Devices for its use, nor for any  
infringem ents of patents or other rights of third parties which m ay result from its use.  
No license is granted by im plication or otherwise under any patent or patent rights of  
Analog Devices.  
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.  
Tel: 781-329-4700 Fax: 781-326-8703  

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