Datasheet > 信号电路 > 锁相环或频率合成电路> ADF4193BCPZ-RL7

ADF4193BCPZ-RL7

更新时间： 2024-01-02 02:41:10

品牌	Logo	应用领域
亚德诺 - ADI		信号电路锁相环或频率合成电路信息通信管理
页数	文件大小	规格书
28页	595K
描述
Low Phase Noise, Fast Settling PLL Frequency Synthesizer

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技术参数
数据手册

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ADF4193BCPZ-RL7 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN, LCC32,.2SQ,20	针数：	32
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.67
Is Samacsys：	N	模拟集成电路 - 其他类型：	PLL FREQUENCY SYNTHESIZER
JESD-30 代码：	S-XQCC-N32	JESD-609代码：	e3
长度：	5 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	32
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装等效代码：	LCC32,.2SQ,20	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
电源：	3 V	认证状态：	Not Qualified
座面最大高度：	1 mm	子类别：	PLL or Frequency Synthesis Circuits
最大供电电流 (Isup)：	27 mA	最大供电电压 (Vsup)：	3.3 V
最小供电电压 (Vsup)：	2.7 V	标称供电电压 (Vsup)：	3 V
表面贴装：	YES	技术：	BICMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	5 mm	Base Number Matches：	1

ADF4193BCPZ-RL7 数据手册

ADF4193

These spurs are attenuated by the loop filter and are more

noticeable on channels close to integer multiples of the refer-

ence where the difference frequency can be inside the loop

bandwidth, thus the name integer boundary spurs.

Table 8. Power-Up Initialization Sequence

Step

Bits

Codes

Description

R5 [7:0]

R3 [15:0] 005B

Set all power-down bits.

PD polarity = 1, ground CP_OUT+

The 8:1 loop bandwidth switching ratio of the ADF4193 makes

it possible to attenuate all spurs to sufficiently low levels for

most applications. The final loop BW can be chosen to ensure

that all spurs are far enough out of band while meeting the lock

time requirements with the 8× bandwidth boost.

CP_OUT–.

Allow time for loop filter

capacitors to discharge.

Clear test modes.

Initialize PLL modes, digital lock

detect on MUX_OUT

Wait

10 ms

R7 [15:0] 0007

R6 [15:0] 000E

The ADF4193’s programmable modulus and R divider can also

be used to avoid integer boundary channels. This option is

described in the Avoiding Integer Boundary Channels section.

R6 [15:0] 900E

10 ns lock detect threshold,

digital lock detect on MUX_OUT

R4 [23:0] 004464 SW1/SW2 timer = 10.8 μs.

R4 [23:0] 00446C SW3 timer = 10.8 μs.

R4 [23:0] 004394 ICP timer = 8.6 μs.

Reference Spurs

Reference spurs are generally not a problem in fractional-N

synthesizers as the reference offset is far outside the loop

bandwidth. However, any reference feedthrough mechanism

that bypasses the loop can cause a problem. One such

mechanism is feedthrough of low levels of on-chip reference

switching noise out through the RF_INpin back to the VCO,

resulting in reference spur levels as high as –90 dBc. These

spurs can be suppressed below –110 dBc by inserting sufficient

reverse isolation, for example, through an RF buffer between

the VCO and RF_INpin. In addition, care should be taken in the

PCB layout to ensure that the VCO is well separated from the

input reference to avoid a possible feedthrough path on the board.

R2 [15:0] 00D2

R1 [23:0] 520209 8/9 prescaler, doubler disabled,

R = 4, toggle FF on, MOD = 65.

R0 [23:0] 480140 INT = 144, FRAC = 40 for

1880 MHz output frequency.

R3 [15:0] 007B

Phase = 26.

PD polarity = 1, release CP_OUT+/

CP_OUT–.

Clear all power-down bits.

R5 [7:0] 05

R0 [23:0] 480140 INT = 144, FRAC = 40 for

1880 MHz output frequency.

The ADF4193 powers up after Step 13. It locks to the

programmed channel frequency after Step 14.

POWER-UP INITIALIZATION

CHANGING THE FREQUENCY OF THE PLL AND THE

PHASE LOOK-UP TABLE

After applying power to the ADF4193, a 14-step sequence is

recommended, as described in Table 8.

Once the ADF4193 is initialized, a write to Register R0 is all

that is required to program a new output frequency. The N

divider is updated with the values of INT and FRAC on the next

PFD cycle following the LE edge that latches in the R0 word.

However, the settling time and spurious performance of the

synthesizer can be further optimized by modifying R1 and R2

are double buffered by the write to R0. This means that while

the data is loaded in through the serial interface on the

respective R1 and R2 write cycles, the synthesizer is not

updated with their data until the next write to Register R0.

The divider and timer setting used in the example in Table 8 is

for a DCS1800 Tx synthesizer with a 104 MHz REF_INfrequency.

The R2 register can be used to digitally adjust the phase of the

VCO output relative to the reference edge. The phase can be

adjusted over the full 360° range at RF with a resolution of

360°/MOD. In most frequency synthesizer applications, the

actual phase offset of the VCO output with respect to the

reference is unknown and does not matter. In such applications,

the phase adjustment capability of the R2 register can instead be

used to optimize the settling time performance, as described in

the Phase Look-Up Table section.

Rev. B | Page 23 of 28

1...20 21 222324 25 26...28

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与ADF4193BCPZ-RL7相关器件

型号	品牌	描述	获取价格	数据表
ADF4196	ADI	Low Phase Noise, Fast Settling, 6 GHz	获取价格
ADF4196BCPZ	ADI	Low Phase Noise, Fast Settling, 6 GHz	获取价格
ADF4196BCPZ-RL7	ADI	Low Phase Noise, Fast Settling, 6 GHz	获取价格
ADF4206	ADI	Dual RF PLL Frequency Synthesizers	获取价格
ADF4206BCHIPS	ADI	IC PLL FREQUENCY SYNTHESIZER, 500 MHz, UUC, DIE, PLL or Frequency Synthesis Circuit	获取价格
ADF4206BRU	ADI	Dual RF PLL Frequency Synthesizers	获取价格

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