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ADF4206BRU

更新时间: 2024-11-30 22:40:31
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20页 207K
描述
Dual RF PLL Frequency Synthesizers

ADF4206BRU 数据手册

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a
Dual RF PLL Frequency Synthesizers  
ADF4206/ADF4207/ADF4208  
GENERAL DESCRIPTION  
FEATURES  
The ADF4206 family of dual frequency synthesizers can be  
used to implement local oscillators in the upconversion and  
downconversion sections of wireless receivers and transmitters.  
Each synthesizer consists of a low-noise digital PFD (Phase  
Frequency Detector), a precision charge pump, a programmable  
reference divider, programmable A and B counters and a dual-  
modulus prescaler (P/P + 1). The A (6-bit) and B (11-bit)  
counters, in conjunction with the dual modulus prescaler (P/P + 1),  
implement an N divider (N = BP + A). In addition, the 14-bit  
reference counter (R Counter), allows selectable REFIN frequen-  
cies at the PFD input. The on-chip oscillator circuitry allows  
the reference input to be derived from crystal oscillators.  
ADF4206: 550 MHz/550 MHz  
ADF4207: 1.1 GHz/1.1 GHz  
ADF4208: 2.0 GHz/1.1 GHz  
2.7 V to 5.5 V Power Supply  
Selectable Charge Pump Supply (VP) Allows Extended  
Tuning Voltage in 3 V Systems  
Selectable Charge Pump Currents  
On-Chip Oscillator Circuit  
Selectable Dual Modulus Prescaler  
RF2: 32/33 or 64/65  
RF1: 32/33 or 64/65  
3-Wire Serial Interface  
Power-Down Mode  
A complete PLL (Phase-Locked Loop) can be implemented if  
the synthesizers are used with an external loop filter and VCOs  
(Voltage Controlled Oscillators).  
APPLICATIONS  
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)  
Base Stations for Wireless Radio (GSM, PCS, DCS,  
CDMA, WCDMA)  
Wireless LANS  
Communications Test Equipment  
CATV Equipment  
Control of all the on-chip registers is via a simple 3-wire interface.  
The devices operate with a power supply ranging from 2.7 V  
to 5.5 V and can be powered down when not in use.  
FUNCTIONAL BLOCK DIAGRAM  
V
1
V
2
V 1  
V 2  
P
DD  
DD  
P
N = BP + A  
ADF4206/ADF4207/ADF4208  
11-BIT RF2  
B-COUNTER  
PHASE  
COMPARATOR  
RF2  
A
B
IN  
RF2  
PRESCALER  
RF2  
CHARGE  
PUMP  
IN  
CP  
RF2  
6-BIT RF2  
A-COUNTER  
RF2  
LOCK  
DETECT  
OSC  
IN  
OSCILLATOR  
OSC  
OUT  
14-BIT RF2  
R-COUNTER  
OUTPUT  
MUX  
MUXOUT  
CLOCK  
DATA  
LE  
22-BIT  
DATA  
REGISTER  
SDOUT  
RF1  
14-BIT RF1  
R-COUNTER  
LOCK  
DETECT  
N = BP + A  
CHARGE  
PUMP  
CP  
RF1  
11-BIT RF1  
B-COUNTER  
PHASE  
COMPARATOR  
RF1  
A
B
IN  
RF1  
PRESCALER  
RF1  
IN  
6-BIT RF1  
A-COUNTER  
AGND  
RF1  
DGND  
RF2  
AGND  
RF2  
DGND  
RF1  
REV. 0  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 2001  

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