Datasheet > ADF4158_18

ADF4158_18

更新时间： 2022-02-26 14:07:29

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
35页	561K
描述
Direct Modulation/Waveform Generating Fractional-N Frequency Synthesizer

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ADF4158_18 数据手册

Data Sheet

ADF4158

C Version¹

Typ

Parameter

Min

Max

Unit

Test Conditions/Comments

NOISE CHARACTERISTICS

Normalized Phase Noise Floor

−216

−110

dBc/Hz

PLL loop bandwidth = 500 kHz;

measured at 100 kHz offset

100 kHz offset; normalized to 1 GHz

At VCO output

(PN_SYNTH

)

Normalized 1/f Noise (PN_{1_f}

Phase Noise Performance⁶

5805 MHz Output⁷

)

−93

dBc/Hz

At 5 kHz offset, 32 MHz PFD frequency

¹Operating temperature for C version: −40°C to +125°C.

²AC coupling ensures AV_DD/2 bias.

³Guaranteed by design. Sample tested to ensure compliance.

⁴The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider

value) and 10 log(f_PFD). PN_SYNTH= PN_TOT− 10 log(f_PFD) − 20 log(N).

⁵The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, f_RF

and at a frequency offset f is given by PN = PN_{1_f}+ 10 log(10 kHz/f) + 20 log(f_RF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL™.

⁶The phase noise is measured with the EVAL-ADF4158EB1Z and the Agilent E5052A phase noise system.

⁷f_REFIN= 128 MHz; f_PFD= 32 MHz; offset frequency = 5 kHz; RF_OUT= 5805 MHz; INT = 181; FRAC = 13631488; loop bandwidth = 100 kHz.

TIMING SPECIFICATIONS

AV_DD= DV_DD= SDV_DD= 2.7 V to 3.3 V; V_P= AV_DDto 5.5 V; AGND = DGND = SDGND = 0 V; T_A= T_MINto T_MAX, dBm referred to 50 Ω,

unless otherwise noted.

Table 2. Write Timing

Parameter

Limit at T_MINto T_MAX(C Version)

Unit

Test Conditions/Comments

LE setup time

DATA to CLK setup time

DATA to CLK hold time

CLK high duration

CLK low duration

t₁

t₂

t₃

t₄

t₅

t₆

t₇

ns min

CLK to LE setup time

LE pulse width

Write Timing Diagram

t₄

t₅

CLK

t₂

t₃

DB2

(CONTROL BIT C3)

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

DB31 (MSB)

DB30

DATA

t₇

t₁

t₆

Figure 2. Write Timing Diagram

Rev. I | Page 5 of 35

1 2 3 456 7 8...35

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