Direct Modulation/Fast Waveform Generating,
13 GHz, Fractional-N Frequency Synthesizer
Data Sheet
ADF4159
FEATURES
GENERAL DESCRIPTION
RF bandwidth to 13 GHz
High and low speed FMCW ramp generation
The ADF4159 is a 13 GHz, fractional-N frequency synthesizer
with modulation and both fast and slow waveform generation
25-bit fixed modulus allows subhertz frequency resolution
PFD frequencies up to 110 MHz
capability. The part uses a 25-bit fixed modulus, allowing subhertz
frequency resolution.
Normalized phase noise floor of −224 dBc/Hz
FSK and PSK functions
Sawtooth, triangular, and parabolic waveform generation
Ramp superimposed with FSK
Ramp with 2 different sweep rates
Ramp delay, frequency readback, and interrupt functions
Programmable phase control
2.7 V to 3.45 V analog power supply
1.8 V digital power supply
Programmable charge pump currents
3-wire serial interface
Digital lock detect
ESD performance: 3000 V HBM, 1000 V CDM
Qualified for automotive applications
The ADF4159 consists of a low noise digital phase frequency
detector (PFD), a precision charge pump, and a programmable
reference divider. The Σ-Δ-based fractional interpolator allows
programmable fractional-N division. The INT and FRAC registers
define an overall N divider as N = INT + (FRAC/225).
The ADF4159 can be used to implement frequency shift keying
(FSK) and phase shift keying (PSK) modulation. Frequency sweep
modes are also available to generate various waveforms in the
frequency domain, for example, sawtooth and triangular wave-
forms. Sweeps can be set to run automatically or with each step
manually triggered by an external pulse. The ADF4159 features
cycle slip reduction circuitry, which enables faster lock times
without the need for modifications to the loop filter.
Control of all on-chip registers is via a simple 3-wire interface. The
ADF4159 operates with an analog power supply in the range of
2.7 V to 3.45 V and a digital power supply in the range of 1.62 V
to 1.98 V. The device can be powered down when not in use.
APPLICATIONS
FMCW radars
Communications test equipment
Communications infrastructure
FUNCTIONAL BLOCK DIAGRAM
AV
DV
SDV
V
R
SET
DD
DD
DD
P
ADF4159
SW2
CP
REFERENCE
5-BIT
R COUNTER
×2
REF
IN
DOUBLER
÷2
DIVIDER
+
–
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
HIGH-Z
CSR
DGND
LOCK
DETECT
FAST LOCK
SWITCH
SW1
OUTPUT
MUX
MUXOUT
SD
DV
OUT
DD
R
DIV
DIV
+
–
RF
RF
A
B
IN
N COUNTER
N
IN
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
CE
TX
DATA
CLK
FRACTION
VALUE
MODULUS
25
VALUE
INTEGER
VALUE
32-BIT
DATA
REGISTER
DATA
LE
2
AGND
DGND
SDGND
CPGND
Figure 1.
Rev. E
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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