Datasheet > ADF4158_18

ADF4158_18

更新时间： 2022-02-26 14:07:29

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
35页	561K
描述
Direct Modulation/Waveform Generating Fractional-N Frequency Synthesizer

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ADF4158_18 数据手册

ADF4158

Data Sheet

Fast Lock Loop Filter Topology

FAST LOCK MODE

To use fast lock mode, an extra connection from the PLL to the

loop filter is needed. The damping resistor in the loop filter must

be reduced to ¼ of its value in wide bandwidth mode. This

reduction is required because the charge pump current is

increased by 16 in wide bandwidth mode, and stability must be

ensured.

The ADF4158 can operate in fast lock mode. In this mode, the

charge pump current is boosted and additional resistors are

connected to maintain the stability of the loop.

Fast Lock Timer and Register Sequences

When fast lock mode is enabled (Register R4, DB[20:19]), after

a write to Register R0, the PLL operates in a wide bandwidth

mode for a selected amount of time. Before fast lock is enabled,

the initialization sequence must be performed after the part is

first powered up (see the Initialization Sequence section). The

time in bandwidth mode is set by:

To further enhance stability and mitigate frequency overshoot

during a frequency change in wide bandwidth mode, Resistor R3

is connected (see Figure 46). During fast lock, the SW1 pin is

shorted to ground, and the SW2 pin is connected to CP (set

Bits DB[20:19] in Register R4 to 01 for fast lock divider).

CLK₁× CLK₂/f_PFD= Time in Wide Bandwidth

The following two topologies can be used:

where:

•

Divide the damping resistor (R1) into two values (R1 and

R1A) that have a ratio of 1:3 (see Figure 46).

CLK₁= Register R2, DB[14:3].

CLK₂= Register R4, DB[18:7].

•

Connect an extra resistor (R1A) directly from SW1 (see

Figure 47). The extra resistor must be selected such that the

parallel combination of an extra resistor and the damping

resistor (R1) is reduced to ¼ of the original value of R1.

_PFD= the PFD frequency.

Note that the fast lock feature does not work in ramp mode.

Fast Lock Example

In this example, the PLL has f_PFDof 100 MHz and requires being

in wide bandwidth mode for 12 µs.

For both topologies, the ratio R3:R2 must equal 1:4.

ADF4158

CLK₁× CLK₂/f_PFD= 12 µs

SW2

CLK₁× CLK₂= (12 × 10⁻⁶)(100 × 10⁶) = 1200

VCO

Therefore, CLK₁= 12 and CLK₂= 100, which results in 12 µs.

SW1

R1A

Figure 46. Fast-Lock Loop Filter Topology—Topology 1

ADF4158

SW2

VCO

R1A

SW1

Figure 47. Fast-Lock Loop Filter Topology—Topology 2

For more fast lock topologies, see ADIsimPLL.

Rev. I | Page 32 of 35

1...29 30 313233 34 35

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与ADF4158_18相关器件

型号	品牌	获取价格	描述	数据表
ADF4158CCPZ	ADI	获取价格	Direct Modulation/Waveform Generating, 6.1 GHz Fractional-N Frequency Synthesizer
ADF4158CCPZ-RL7	ADI	获取价格	Direct Modulation/Waveform Generating, 6.1 GHz Fractional-N Frequency Synthesizer
ADF4158WCCPZ	ADI	获取价格	Direct Modulation/Waveform Generating, 6.1 GHz Fractional-N Frequency Synthesizer
ADF4158WCCPZ-RL7	ADI	获取价格	Direct Modulation/Waveform Generating Fractional-N Frequency Synthesizer
ADF4159	ADI	获取价格	Direct Modulation/Fast Waveform Generating, 13 GHz, Fractional-N Frequency Synthesizer
ADF4159_14	ADI	获取价格	Direct Modulation/Fast Waveform Generating,
ADF4159CCPZ	ADI	获取价格	Direct Modulation/Fast Waveform Generating, 13 GHz, Fractional-N Frequency Synthesizer
ADF4159CCPZ-RL7	ADI	获取价格	Direct Modulation/Fast Waveform Generating, 13 GHz, Fractional-N Frequency Synthesizer
ADF4159WCCPZ	ADI	获取价格	Direct Modulation/Fast Waveform Generating,
ADF4159WCCPZ-RL7	ADI	获取价格	Direct Modulation/Fast Waveform Generating,

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