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ADF4157BCPZ-RL

更新时间： 2024-02-06 17:43:44
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
24页 365K
描述
High Resolution 6 GHz Fractional-N Frequency Synthesizer

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ADF4157BCPZ-RL 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFN
包装说明：HVQCCN, LCC20,.16SQ,20针数：20
Reach Compliance Code：compliantECCN代码：5A991.B
HTS代码：8542.39.00.01风险等级：5.43
模拟集成电路 - 其他类型：PLL FREQUENCY SYNTHESIZERJESD-30 代码：S-XQCC-N20
JESD-609代码：e3长度：4 mm
湿度敏感等级：3功能数量：1
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装等效代码：LCC20,.16SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：3.3/5.5 V
认证状态：Not Qualified座面最大高度：1 mm
子类别：PLL or Frequency Synthesis Circuits最大供电电流 (Isup)：29 mA
最大供电电压 (Vsup)：3.3 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：4 mm
Base Number Matches：1

ADF4157BCPZ-RL 数据手册

 浏览型号ADF4157BCPZ-RL的Datasheet PDF文件第2页浏览型号ADF4157BCPZ-RL的Datasheet PDF文件第3页浏览型号ADF4157BCPZ-RL的Datasheet PDF文件第4页浏览型号ADF4157BCPZ-RL的Datasheet PDF文件第5页浏览型号ADF4157BCPZ-RL的Datasheet PDF文件第6页浏览型号ADF4157BCPZ-RL的Datasheet PDF文件第7页 
High Resolution 6 GHz Fractional-N  
Frequency Synthesizer  
Data Sheet  
ADF4157  
FEATURES  
GENERAL DESCRIPTION  
RF bandwidth to 6 GHz  
25-bit fixed modulus allows subhertz frequency resolution  
2.7 V to 3.3 V power supply  
Separate VP allows extended tuning voltage  
Programmable charge pump currents  
3-wire serial interface  
Digital lock detect  
Power-down mode  
Pin compatible with the following frequency synthesizers:  
ADF4110/ADF4111/ADF4112/ADF4113/  
ADF4106/ADF4153/ADF4154/ADF4156  
Cycle slip reduction for faster lock times  
The ADF4157 is a 6 GHz fractional-N frequency synthesizer with  
a 25-bit fixed modulus, allowing subhertz frequency resolution  
at 6 GHz. It consists of a low noise digital phase frequency detector  
(PFD), a precision charge pump, and a programmable reference  
divider. There is a Σ-Δ based fractional interpolator to allow  
programmable fractional-N division. The INT and FRAC values  
define an overall N divider, N = INT + (FRAC/225). The ADF4157  
features cycle slip reduction circuitry, which leads to faster lock  
times without the need for modifications to the loop filter.  
Control of all on-chip registers is via a simple 3-wire interface.  
The device operates with a power supply ranging from 2.7 V to  
3.3 V and can be powered down when not in use.  
APPLICATIONS  
Satellite communications terminals, radar equipment  
Instrumentation equipment  
Personal mobile radio (PMR)  
Base stations for mobile radio  
Wireless handsets  
FUNCTIONAL BLOCK DIAGRAM  
AV  
DD  
DV  
DD  
V
R
SET  
P
ADF4157  
REFERENCE  
5-BIT  
R COUNTER  
×2  
REF  
IN  
DOUBLER  
÷2  
DIVIDER  
+
PHASE  
CP  
CHARGE  
PUMP  
FREQUENCY  
DETECTOR  
–
V
DD  
HIGH Z  
CSR  
DGND  
LOCK  
DETECT  
CURRENT  
SETTING  
OUTPUT  
MUX  
MUXOUT  
SD  
OUT  
V
DD  
RFCP4 RFCP3 RFCP2 RFCP1  
R
DIV  
DIV  
RF  
RF  
A
B
IN  
N COUNTER  
N
IN  
THIRD-ORDER  
FRACTIONAL  
INTERPOLATOR  
CE  
CLK  
DATA  
LE  
FRACTION MODULUS  
INTEGER  
REG  
32-BIT  
DATA  
REGISTER  
25  
REG  
2
AGND  
DGND  
CPGND  
Figure 1.  
Rev. D  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 www.analog.com  
Fax: 781.461.3113 ©2007–2012 Analog Devices, Inc. All rights reserved.  
 
 
 
 
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