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ADF4158

更新时间： 2024-01-21 16:40:12
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
36页 437K
描述
Direct Modulation/Waveform Generating, 6.1 GHz Fractional-N Frequency Synthesizer

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ADF4158 技术参数

Source Url Status Check Date：2013-05-01 14:56:35.841是否无铅： 含铅
是否Rohs认证： 符合生命周期：Active
包装说明：QCCN, LCC24,.16SQ,20针数：24
Reach Compliance Code：compliantECCN代码：5A991.B
HTS代码：8542.39.00.01风险等级：2.22
模拟集成电路 - 其他类型：PLL FREQUENCY SYNTHESIZERJESD-30 代码：S-PQCC-N24
端子数量：24最高工作温度：125 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：QCCN封装等效代码：LCC24,.16SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3 V
认证状态：Not Qualified子类别：PLL or Frequency Synthesis Circuits
最大供电电流 (Isup)：32 mA标称供电电压 (Vsup)：3 V
表面贴装：YES技术：BICMOS
温度等级：AUTOMOTIVE端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIEDBase Number Matches：1

ADF4158 数据手册

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Direct Modulation/Waveform Generating,  
6.1 GHz Fractional-N Frequency Synthesizer  
ADF4158  
FEATURES  
GENERAL DESCRIPTION  
RF bandwidth to 6.1 GHz  
The ADF4158 is a 6.1 GHz, fractional-N frequency synthesizer  
25-bit fixed modulus allows subhertz frequency resolution  
Frequency and phase modulation capability  
Sawtooth and triangular waveforms in the frequency domain  
Parabolic ramp  
Ramp superimposed with FSK  
Ramp with 2 different sweep rates  
Ramp delay  
Ramp frequency readback  
Ramp interruption  
2.7 V to 3.3 V power supply  
Separate VP allows extended tuning voltage  
Programmable charge pump currents  
3-wire serial interface  
Digital lock detect  
Power-down mode  
with modulation and waveform generation capability. It con-  
tains a 25-bit fixed modulus, allowing subhertz resolution at  
6.1 GHz. It consists of a low noise digital phase frequency  
detector (PFD), a precision charge pump, and a programmable  
reference divider. There is a sigma-delta (Σ-Δ) based fractional  
interpolator to allow programmable fractional-N division. The  
INT and FRAC registers define an overall N-divider as N = INT  
+ (FRAC/225).  
The ADF4158 can be used to implement frequency shift keying  
(FSK) and phase shift keying (PSK) modulation. There are also  
a number of frequency sweep modes available, which generate  
various waveforms in the frequency domain, for example,  
sawtooth and triangular waveforms. The ADF4158 features  
cycle slip reduction circuitry, which leads to faster lock times,  
without the need for modifications to the loop filter.  
Cycle slip reduction for faster lock times  
Switched bandwidth fast-lock mode  
Control of all on-chip registers is via a simple 3-wire inter-  
face. The device operates with a power supply ranging from  
2.7 V to 3.3 V and can be powered down when not in use.  
APPLICATIONS  
FMCW radar  
Communications test equipment  
FUNCTIONAL BLOCK DIAGRAM  
AV  
DD  
DV  
DD  
V
R
SET  
P
ADF4158  
SW2  
CP  
REFERENCE  
5-BIT  
R-COUNTER  
×2  
REF  
IN  
DOUBLER  
÷2  
DIVIDER  
+
PHASE  
CHARGE  
PUMP  
FREQUENCY  
DETECTOR  
V
DD  
–
HIGH-Z  
CSR  
DGND  
LOCK  
DETECT  
SW1  
FL SWITCH  
O
OUTPUT  
MUX  
MUXOUT  
CE  
V
DD  
R
N
DIV  
DIV  
RF  
A
B
IN  
N-COUNTER  
TX  
DATA  
RF  
IN  
THIRD-ORDER  
FRACTIONAL  
INTERPOLATOR  
CLK  
MODULUS  
25  
2
FRACTION  
REG  
INTEGER  
REG  
32-BIT  
DATA  
REGISTER  
DATA  
LE  
AGND  
DGND  
CPGND  
Figure 1.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2010 Analog Devices, Inc. All rights reserved.  
 
 
 
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